Electronic Abacus (e-Abacus) using FPGA Altera DE2 Board

Abstract

The development of electronic abacus using Altera DE2 115, is to integrate the use of abacus along with electronic devices which offer better visualisation of the abacus operations. The main focus of this technology is to assist the primary school students in validating a fundamental arithmetic operation. The electronic abacus is developed by integrating an abacus, abacus decoder module and field programming gate array (FPGA) based processor. DE2 115 is chosen as the development module and very high-speed integrated circuit hardware description language (VHDL) as a main programming language. The arithmetic algorithm developed for the electronic abacus is limited to the computational of whole numbers only, involving the basic arithmetic operation of additional, subtraction, multiplication and division. This electronic abacus comes with two operational modes, display and arithmetic mode. In the display mode, the abacus beads position at column one until column seven is displayed as numerical representation on the liquid crystal display (LCD) screen. A computation of arithmetic operations with less than three operators is available in the arithmetic mode with the capability of displaying the negative numerical and infinite value. From the simulation conducted in Quartus II, the implementation of the algorithm in FPGA utilise 4% from the total logical element allowed and consume approximately 143.4 mW of power. As a conclusion, this enhanced ancient apparatus hopefully will contribute to the development of more lively and interesting teaching approach.