Vertical PN Junction Research Articles

Enhanced solar hydrogen evolution by laminated integration of n+p-SiIP/TiO2/Pt inverted pyramid black Si photocathode

The nano/microstructuring of silicon (Si) via chemical methods has garnered significant attention due to its excellent light-trapping capabilities across a wide spectral range. Current research has predominantly focused on the synthesis of pyramidal-shaped microtextures, which enable two reflections on the surface, while largely overlooking the superior light-trapping potential of inverted pyramid silicon (SiIP) microtextures, which theoretically allow for three reflections. Moreover, there has been limited investigation into the application of inverted pyramid black silicon for solar-driven hydrogen evolution. This study reports the synthesis of uniformly arranged inverted pyramid-textured black silicon using the copper-assisted chemical etching (Cu-ACE) method to enhance the efficiency of solar-driven water splitting for hydrogen production. The formation mechanism and the influence of copper-localized surface plasmon resonance (Cu-LSPR) from Cu nanoparticle (NP) byproducts on photoelectrochemical (PEC) activity were systematically analyzed. To reduce sidewall defects and minimize photogenerated carrier recombination, the surface of the SiIP was treated with tetramethylammonium hydroxide (TMAH). A vertical PN junction was developed through ion implantation to reduce the external bias of the SiIP. Additionally, a uniform TiO₂ antireflective layer was deposited via atomic layer deposition (ALD), reducing the average reflectance of the SiIP-T4 to 5.78 % over the 300–1100 nm wavelength range. MoSₓ and Pt NPs were electrodeposited to improve the fill factor and enhance HER kinetics. With optimized catalyst loading, the n+p-SiIP-T4/TiO₂/Pt 80 mC electrode achieved a photocurrent density of 8.0 mA cm−2 at 0 V vs. RHE, an applied bias photon-to-current efficiency (ABPE) of 0.93 % at 0.24 V vs. RHE, and a double-layer capacitance (Cdl) of 91 μF cm−2. The onset potential (Von) was positively shifted by ∼1.13 V to 0.49 V vs. RHE compared to a SiIP photocathode, and the photocathode operated continuously at 0 V vs. RHE for 27 h in an acidic electrolyte. These results demonstrate that SiIP has significant potential for PEC hydrogen evolution, with further performance optimization achievable through structural and surface engineering.

High modulation efficiency sinusoidal vertical PN junction phase shifter in silicon-on-insulator

In this paper, a sinusoidal vertical PN junction phase shifter on a silicon waveguide is designed, and the results demonstrate that modifying the shape of the PN junction significantly increases the area of the depletion region within the standard waveguide width of 500 nm, thereby enhancing the overlap between the depletion region and optical waveguide modes under reverse bias conditions. Furthermore, by adjusting the sinusoidal amplitude (A) of the doping contact interface, it is observed that when A=0.065µm, the resulting sinusoidal PN junction most effectively enhances the interaction between carriers and photons, leading to the highest modulation efficiency and the lowest loss. Based on this, further adjustment of the doping concentration distribution in the waveguide was conducted using a doping compensation method. It is observed that setting the doping concentration at 3×1018cm−3 in the heavily doped region and at 1×1018cm−3 in the lightly doped region enables the phase shifter to achieve high modulation efficiency while maintaining low loss. This is attributed to the highest optical intensity being concentrated in the central region of the waveguide, as well as to the positive correlation between doping concentration and modulation efficiency. The final designed device with a length of 1.5 mm successfully attained a low V π L of 0.58V⋅cm, resulting in high modulation efficiency. By employing traveling wave electrodes and ensuring that the effective refractive index of the radio frequency (RF) matches the optical group index (OGI), circuit-level simulations were conducted. The device exhibited a 3 dB bandwidth of 8.85 GHz and eye diagrams of up to 40 Gbit/s, with a maximum extinction ratio (ER) of 8.27 dB and a bit error rate (BER) of 8.83×10−6, which can be widely used in the field of high-speed silicon optical modules.

Modulation of Diamond PN Junction Diode with Double-Layered n-Type Diamond by Using TCAD Simulation

This study proposed a novel double-layer junction termination structure for vertical diamond-based PN junction diodes (PND). The effects of the geometry and doping concentration of the junction termination structure on the PNDs’ electrical properties are investigated using Silvaco TCAD software (Version 5.0.10.R). It demonstrates that the electric performances of PND with a single n-type diamond layer are sensitive to the doping concentration and electrode location of the n-type diamond. To further suppress the electric field crowding and obtain a better balance between breakdown voltage and on-resistance, a double-layer junction termination structure is introduced and evaluated, yielding significantly improved electronic performances. Those results provide some useful thoughts for the design of vertical diamond PND devices.

Interface engineering by constructing vertical junction for reduced noise and improved sensitivity in 2D photodetector

Two-dimensional (2D) materials have been widely demonstrated as promising candidates for next generation photodetectors, while the noticeable channel current is still a limiting factor for photodetection sensitivity. In this work, the interface engineering has been developed by constructing a vertical pn and Schottky junction in the 2D WS2 channel, resulting in a reduced dark current and noise spectral density, significantly improving the sensitivity. Specifically, the WS2 bottom surface is coupled with p-type tellurium (Te) nanoribbon and gold (Au) stripes, thus a vertical pn and Schottky junction can be constructed at WS2/Te and WS2/Au interface, respectively. In both device architectures, the dark current and electric noise are much suppressed due to the formation of depletion region in WS2 channel. Meanwhile, the out-of-plane built-in electric field at junction can facilitate the separation of photo-excited electron–hole pairs, which subsequently yields a faster temporal response. For the WS2/Au device, the incident light can be reflected by the bottom Au and propagate through the WS2 layer again, further boosting the photo-absorption, thus the photodetection sensitivity. The engineered WS2 photodetectors exhibit the noise spectral density as low as 5.36 × 10−14 A Hz−1/2 and high specific detectivity (D*) up to 1.12 × 1011 Jones, which has one–two orders of magnitude improvement compared to the pristine device. This work provides an effective and universal interface engineering strategy to achieve low noise and high sensitivity in 2D photodetectors.

Ultralow-Power Double Vertical Junction Microdisk Modulators

One of the most critical elements in a data center transceiver is the optoelectronic modulator. In a silicon-based optoelectronic modulator, the ultimate performance depends on the orientation and positioning of its pn junction(s). In comparison to a conventional, lateral pn junction, a vertical pn junction improves energy efficiency by having a stronger overlap with the resonant optical signal. Adding to this design philosophy, we present two new designs of vertical junction modulators: (i) a double vertical junction, which doubles the interaction length, and (ii) a staggered double vertical junction, which further increases the interaction length by adding a lateral component to the double junction design. In this work, we provide a comprehensive numerical comparison of microring/disk modulators between the conventional, lateral pn junction and our vertical pn junction designs. We demonstrate how our new double vertical junction configurations offer the most promising power performance characteristics, with an energy-efficiency improvement by over a factor of 4. Our work may pave the way for new, energy-efficient silicon modulators in next-generation information processing and communications.

Ultrafast electro-optical disk modulators for logic, communications, optical repeaters, and wavelength converters.

We propose a U-shaped pn junction in a silicon-on-insulator microdisk resonator to effectively double the junction-mode overlap in the state-of-the-art, vertical pn junction microdisk electro-optical (EO) modulators. The U-shaped pn junction promotes the maximum overlap between the junction depletion zone and the whispering gallery optical mode in the microdisk. By fully depleting the p region of the npn-sequenced U-junction, the capacitance is reduced below 3 fF, which significantly improves the speed and power performance. In this work, we implement the high-efficiency, depleted U-junction design to maximize the operating bandwidth of EO modulators, EO logic elements, EO 2 × 2 switches for wavelength-division cross-connects, 2 × 2 reconfigurable optical add-drop multiplexers, optical-to-electrical-to-optical (OEO) repeaters-with-gain, OEO wavelength converters, and 2 × 2 optical-optical logic gates. These devices all operate in the 7.6-to-50 GHz bandwidth range with ultralow energy consumption between 0.4 and 9.8 fJ/bit. By using CMOS-compatible materials and fabrication-feasible design dimensions, our proposed high-performance devices offer a promising potential in next-generation, high-volume electro-optical communications and computing circuits.

Evaluation of residual defects created by plasma exposure of Si substrates using vertical and lateral pn junctions

Defect creation in both the vertical and lateral directions of Si substrates during plasma processing has become a critical problem in the fabrication of three-dimensional structural devices. In this study, the authors present pn junction structures that can be used to evaluate defects in both the vertical and lateral directions of a Si substrate. Samples with these pn junction structures were exposed to fluorocarbon plasma; after plasma exposure, a chemical dry etching process was employed to determine the influence of residual species on damaged layer formation, and capacitance–voltage measurements were conducted to detect the formation of defects in the Si substrate. The results confirmed that defects created by plasma exposure act as carrier trapping sites. Spectroscopic ellipsometry and time-of-flight secondary ion mass spectrometry revealed that the damaged layers were tens of nanometers thick, and cathodoluminescence analysis identified the presence of “latent” defects in the damaged layer even after furnace annealing. Moreover, current–voltage measurements of devices with different pn junction distances revealed that leakage current in both the vertical and lateral directions increased with decreasing pn junction distance. The experimental results of this study demonstrate that plasma-induced damage (PID) creates defects in both the vertical and lateral directions; lateral defects are assumed to be caused by the stochastic straggling of incident ions, which has been predicted by molecular dynamic simulations. The implementation of devices with lateral pn junctions is essential in improving the understanding of PID mechanisms and designing future electronic devices that are sensitive to latent defects.

Alignment tolerant, low voltage, 0.23 V.cm, push-pull silicon photonic switches based on a vertical pn junction.

In this paper, we present the design, fabrication and characterization of a carrier depletion silicon-photonic switch based on a highly doped vertical pn junction. The vertical nature of the pn junction enables the device to exhibit a modulation efficiency as high as 0.23 V.cm. Fast switching times of 60ps are achieved in a lumped configuration. Moreover, the process flow is highly tolerant to fabrication deviations allowing a seamless transfer to the 350 nm process node of a commercial complementary-metal-oxide semiconductor (CMOS) foundry. Overall, this work showcases the possibility of fabricating highly efficient carrier depletion-based silicon photonic switches using medium resolution lithography.

Analysis of germanium-doped silicon vertical PN junction optical phase shifter

In this paper, the performance of a germanium-doped silicon optical phase shifter with vertical PN junction has been investigated. The proposed phase shifter is simulated using a process simulation tool, and 2D carrier distribution has been used to calculate the phase shifter performance metrics. The designed phase shifter is integrated into a Mach–Zehnder interferometer structure, and the transfer characteristics are plotted. The proposed phase shifter has a phase shift of ∼141°/mm, VπLπ of ∼0.64 V·cm, insertion loss of ∼1.23 dB, and 3 dB bandwidth of ∼37 GHz at 5 V reverse bias.

Performance analysis of an electrostatic doping assisted silicon microring modulator

Abstract In this paper, we propose and numerically analyze electrostatic doping (ED) assisted silicon microring modulator (MRM) realizable on SOI platform having ∼ 10 nm free spectral range (FSR). The proposed modulator consists of a vertical metal–insulator–semiconductor (MIS) junction and a lateral metal–semiconductor (MS) junction. It utilizes ED to achieve free carriers inside the rib waveguide that eventually introduces the free carrier plasma dispersion effect. The proposed device does not employ any lateral or vertical PN or PIN junction and offers high operating speed with negligible static power consumption. Numerical simulation using commercially available TCAD tools and mode solvers are used to estimate the performance of the proposed modulators. Palladium (Pd) and aluminum (Al) are used as electrodes to realize ED enabled MIS–MS charge plasma diode. The performance of the proposed modulator is extensively studied both in steady state and transient state. Results predict that a maximum 37.8 dB and 33 dB of extinction ratio (ER) is achievable by the modulator while operating in inversion and accumulation mode, respectively. Predicted insertion losses are 1.97 dB and 1.49 dB when operated in inversion and accumulation mode respectively. The proposed modulator is expected to provide a maximum of 26.3 Gbps and 32.2 Gbps operating speed with a 9.21 GHz and 11.29 GHz of 3-dB optical bandwidth in inversion and accumulation mode of operation, respectively. Simulation result predicts that the dynamic energy per bit for the proposed ED assisted MRM is approximately 31 fJ/bit and 68 fJ/bit in inversion and accumulation mode of operation, respectively.

Ultracompact CMOS-compatible optical logic using carrier depletion in microdisk resonators

We present a CMOS-compatible optoelectronic directed logic architecture that achieves high computational throughput (number of operations per second per unit area) by its ultracompact form factor. High speed-to-power performance is also achieved, by the low capacitance and high junction-to-mode overlap of low-radii SOI vertical pn junction microdisk switches. By using wavelength-division multiplexing and two electrical control signals per disk, each switch performs (N)OR, (N)AND, and X(N)OR operations simultaneously. Connecting multiple switches together, we demonstrate higher-order scalability in five fundamental N-bit logic circuits: AND/OR gates, adders, comparators, encoders, and decoders. To the best of our knowledge, these circuits achieve the lowest footprint of silicon-based multigigabit-per-second optical logic devices in literature.

Carbon Nanotube Sheet as Top Contact Electrode for Nanowires: Highly Versatile and Simple Process.

In the past years, lots of research works were dedicated to nanowires and their integration into functional devices. However, despite the great potential of such materials, no device based on nanowires has been transferred in all-day-life. In fact, the vertical device integration is slowed down by the difficulty to contact easily the top electrode. With this work, we present a simple, elegant and versatile process for creating a top electrode contact on nanowires: a carbon nanotube sheet is suspended at the top of the nanowire field. The proof of concept is made through the realization of photovoltaic devices composed of an assembly of vertical PN-junctions based on silicon nanowires. For an illumination density of 100 mW . cm-2, our devices exhibit short circuit current density as high as 15 mA . cm-2. Due to the numerous advantages of the carbon nanotube sheets as top electrode, such as transparency, porosity, good mechanical performance and no need to embed nanowires, such simple and elegant technology should definitely find developments in every field of nanotechnology.

Low loss, high-speed single-mode half-disk resonator.

This work proposes a new type of resonator: a single-mode half-disk resonator. Half of the resonator is solid, allowing large electrical or mechanical contacts, and a single-mode operation can be retained. A systematic design method is demonstrated and analyzed. For a 3 μm radius, the simulation predicts an internal Q-factor as high as 2.4×10⁵, and a loaded Q-factor of ~9000 is measured in experiments, comparable even with uncontacted microrings of bigger radii. The large contacts will improve the performance of a wide range of active devices. We present the contact resistance of a vertical PN junction modulator based on this structure, which can be reduced to nearly an order of magnitude, enabling a much faster modulation speed.

A Vertical PN Junction Utilizing the Impurity Photovoltaic Effect for the Enhancement of Ultra-thin Film Silicon Solar Cells

ABSTRACTWe report a preliminary study on the influence of indium doping on ultra-thin film silicon solar cells. The design of the cell reported here is such that it should elucidate the impact of the indium dopant, which is concentrated in the thin film. Indium, a deep level in silicon (0.157 eV above the valence band), acts as a p-type dopant and a sensitizer. Absorption through sub-bandgap transitions is expected based on the previously reported Impurity PhotoVoltaic (IPV) Effect [1]. It is proposed that the implementation of a novel vertical PN junction configuration together with the IPV effect enhances the efficiency of ultra-thin solar cells. The most efficient cell fabricated to date, in our research group, has a conversion efficiency of 4.3 % (active silicon thickness of 2.5 μm), a short-circuit current density of 14.9 mA/cm2 and an open-circuit voltage of 0.51 V under 1 sun illumination. The cell has not been optimized with any type of light trapping technique and 11.24 % of the cell surface is covered by the metal contacts. Numerical simulation indicates that for the geometry used, the maximum efficiency that may be expected is 9.8 % (compared to the 4.3 % measured).

Adiabatic microring modulators

In this work, we demonstrate and experimentally characterize a new class of high-performance silicon photonic modulators-the adiabatic microring modulator. The adiabatic microring modulator utilizes a vertical PN junction and interior electrical contacts, leveraging all the advantages of previously-demonstrated microdisk modulators. However, this device also incorporates an adiabatic transition from the wide, multimode contact region, to a narrow, single-mode coupling region, eliminating unwanted spatial modes common to microdisks. As a result, the adiabatic microring modulator demonstrated in this work is the smallest microring modulator demonstrated to date, with a diameter of only 4 μm, yielding a 6.92-THz uncorrupted free spectral range. Here, we perform an experimental comparative analysis between silicon adiabatic microring modulators, silicon microdisk modulators, and a commercial lithium-niobate Mach-Zehnder modulator. We show that the silicon adiabatic microring modulator using partial doping is capable of operating at 12.5-Gb/s data rates and beyond. This device combines the best of all modulator designs, leveraging the depletion-based method to maximize the speed, utilizing the vertical-junction configuration to minimize the power consumption, employing a unique adiabatic design to eliminate higher-order modes, and using partial doping to reduce resistance, further enhancing the speed of the device.

Electroluminescence from strained germanium membranes and implications for an efficient Si-compatible laser

We demonstrate room-temperature electroluminescence (EL) from light-emitting diodes (LEDs) on highly strained germanium (Ge) membranes. An external stressor technique was employed to introduce a 0.76% bi-axial tensile strain in the active region of a vertical PN junction. Electrical measurements show an on-off ratio increase of one order of magnitude in membrane LEDs compared to bulk. The EL spectrum from the 0.76% strained Ge LED shows a 100 nm redshift of the center wavelength because of the strain-induced direct band gap reduction. Finally, using tight-binding and finite-difference time domain simulations, we discuss the implications for highly efficient Ge lasers.

A Novel Responsivity Model for Stripe-Shaped Ultraviolet Photodiode

A novel responsivity model, which is based on the solution of transport and continuity equation of carriers generated both in vertical and lateral PN junctions, is proposed for optical properties of stripe-shaped silicon ultraviolet (UV) photodiodes. With this model, the responsivity of the UV photodiode can be estimated. Fabricated in a standard 0.5 μm CMOS process, the measured spectral responsivity of the stripe-shaped UV photodiode shows a good match with the numerical simulation result of the responsivity model at the spectral of UV range. It means that the responsivity model, which is used for stripe-shaped UV photodiode, is reliable.

Spectral response of blue-sensitive Si photodetectors in SOI

In this paper, we present a novel blue-sensitive Si photodetector. The detector is realized as a Si diode with a vertical PN junction in the silicon-on-insulator (SOI) thin film for normal incident light. Due to the thin SOI device layer, the photodetector shows a blue-shift spectral response with the peak external quantum efficiency (QE) of 69.6% at wavelength of 480 nm. The photodetector adopts a thin layer of SiO 2 as an antireflection coating and as a blocking layer for shallow ion implantation doping. The isolation trench etched through the SOI thin film to the buried oxide (BOX) provides fully electrical isolation. The device structure is simple and its performance is very high, therefore, it is in favor of monolithically integration with other micro/nanodevices.