Vertical Nanowire MOSFETs Research Articles

Performance, Analysis, and Modeling of III-V Vertical Nanowire MOSFETs on Si at Higher Voltages

Heterostructure engineering in III-V vertical nanowire (VNW) MOSFETs enables tuning of transconductance and breakdown voltage. In this work, an In_<i>x</i>Ga<inline-formula> <tex-math notation="LaTeX">$_{{1}-{x}}$ </tex-math></inline-formula>As channel with a Ga-composition grading (<inline-formula> <tex-math notation="LaTeX">${x} \,\,=$ </tex-math></inline-formula> 1&#x2013;0.4) in the channel and drain region, combined with field plate engineering, enables breakdown voltage above 2.5 V, while maintaining transconductance of about 1 mS/<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula>, in VNW MOSFETs. The field plate consists of a vertically integrated SiO₂ layer and a gate contact, which screens the electric field in the drain region, extending the device operating voltage. By scaling the field plate, a transconductance of 2 mS/<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula>, alongside the breakdown voltage of 1.5 V, is obtained, demonstrating the benefit of field engineering in the drain. The scalability of the field plate and the gate is measured, showing an ON-resistance increase by 23 <inline-formula> <tex-math notation="LaTeX">$\Omega \cdot \mu \text{m}$ </tex-math></inline-formula>, and transconductance decrease by 5 <inline-formula> <tex-math notation="LaTeX">$\mu \text{S}/\mu \text{m}$ </tex-math></inline-formula>, per nm field plate length. This behavior is captured in a new and modified virtual source model, where device transmission and drain resistance are altered to capture the field plate scaling effect. The modeling is applied to nanowire (NW) devices with field plate lengths ranging from 5 to 115 nm, capturing accurately essential device performance parameters. Finally, a modified band-to-band (BTB) tunneling approach is used to accurately describe the device behavior above 1.5 V.

On the asymmetry of the DC and low-frequency noise characteristics of vertical nanowire MOSFETs with bulk source contact

In this work, the impact of switching the source and drain on the low-frequency noise of Gate-All-Around (GAA) Vertical Nanowire (VNW) n- and pMOSFETs fabricated on bulk silicon wafers is investigated. Switching the role of the electrodes results in an increase in the absolute value of the threshold voltage, a higher subthreshold slope and maximum transconductance. For the p-channel devices, significantly lower 1/f noise is observed in reverse operation compared with the normal forward configuration. Considering the mobility fluctuations origin of the 1/f noise, this indicates a pronounced impact of the choice of the source/drain contact on the conduction in the p-type silicon nanowires. On the other hand, little effect on the noise behaviour has been found from the in-situ boron doping density in the NWs. For the n-channel FETs, qualitatively similar results have been obtained with respect to the 1/f noise PSD. At the same time, the dominant flicker noise mechanism changes from Δμ dominated in F operation to rather Δn in R mode.

A Simulation Study on the Effects of Interface Charges and Geometry on Vertical GAA GaN Nanowire MOSFET for Low-Power Application

The effects of interface charges on the performances of gate-all-around (GAA) GaN vertical nanowire MOSFETs with different geometries have been studied. Geometrical effect on the gate current of vertical GAA GaN nanowire MOSFET has also been analysed for the first time. In the ideal condition, the circular geometry nanowire (CGN) MOSFET exhibits the best performance with subthreshold swing (SS) of 62 mV/dec, drain-induced barrier lowering (DIBL) of 14 mV/V, and ON/OFF current ratio ( I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> ) of ~10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">8</sup> . The triangular or hexagonal geometry nanowire (TGN or HGN) MOSFET suffer from large gate leakage current due to the field enhancement at sidewall corners. It is also known that interface traps at the sidewall surface of vertical nanowires deteriorate the overall device performance. The HGN MOSFET with m-plane sidewall demonstrates the best performance with SS of 69 mV/dec and DIBL of 13 mV/V, while the TGN MOSFET with a-plane sidewall exhibits the worst performance with SS of 112 mV/dec and DIBL of 101 mV/V.

Millimeter-Wave Vertical III-V Nanowire MOSFET Device-to-Circuit Co-Design

Vertical III-V nanowire MOSFETs show potential towards the ultimate transistor scaling. A high transconductance and current density are achieved based on the gate-all-around architecture. This work presents a high-frequency design of such devices, achieving more than 600 GHz cut-off frequencies ( f T, f max), at 20 nm gate length. Furthermore, capacitance design and scaling trends, supported by COMSOL Multiphysics simulations derive state-of-the-art parasitics magnitudes for vertical devices in general, reaching gate-drain capacitance values of 17 aF/wire, corresponding to 0.2 fF/μm. A unique co-designed feedback resonant circuit makes the device unilateral, exhibiting up to 15 dB gain in D-band at 0.5 V supply, and with a current density of 0.5 mA/μm. Finally, a 2-stage low noise amplifier is designed using an optimum matching concept to utilize the full available bandwidth. The resulting circuit performance is independent of transistor gate length, since any decrease in device intrinsic capacitance is assisted by an increase in device overlap capacitances in a setting unique to a current implementation of vertical nanowire MOSFETs. With this approach, amplifiers are designed with more than 20 dB gain and minimum noise figure of 2.5 dB in a simulation environment at 140 GHz. The proposed technology and design platform show a great potential in future low-power communication systems.

Low-Power Resistive Memory Integrated on III–V Vertical Nanowire MOSFETs on Silicon

III-V vertical nanowire MOSFETs (VNW-FETs) have the potential to extend Moore's law owing to their excellent material properties. To integrate highly scaled memory cells coupled with high performance selectors at minimal memory cell area, it is attractive to integrate low-power resistive random access memory (RRAM) cells directly on to III-V VNW-FETs. In this work, we report the experimental demonstration of successful RRAM integration with III-V VNW-FETs. The combined use of VNW-FET drain metal electrode and the RRAM bottom electrode reduces the process complexity and maintains material compatibility. The vertical nanowire geometry allows the RRAM cell area to be aggressively scaled down to 0.01 μ <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m2</sup> enabling realization of dense memory (1T1R) cross-point arrays on silicon.

Vertical nanowire III–V MOSFETs with improved high‐frequency gain

High-frequency performance of vertical InAs/InGaAs heterostructure nanowire MOSFETs on Si is demonstrated for the first time for a gate-last configuration. The device architecture allows highly asymmetric capacitances, which increases the power gain. A device with L g = 120 nm demonstrates f T = 120 GHz, f max = 130 GHz and maximum stable gain (MSG) = 14.4 dB at 20 GHz. These metrics demonstrate the state-of-the-art performance of vertical nanowire MOSFETs.

Effects of Contact Potential and Sidewall Surface Plane on the Performance of GaN Vertical Nanowire MOSFETs for Low-Voltage Operation

GaN-based materials are expected to show excellent immunity against short-channel effects because they have relatively lower permittivity and higher electron effective mass, compared to other materials such as Si, Ge, and In(Ga)As. To further reduce the short-channel effects, it is important to enhance the gate controllability of the device by utilizing a gate-all-around (GAA) structure. In this article, GaN vertical GAA nanowire MOSFETs with various diameters of 120, 75, and 45 nm have been fabricated. The device with a diameter of 120 nm shows a threshold voltage of 0.7 V, drain saturation voltage of 0.5 V, and subthreshold swing of 70 mV/decade, which would be suitable for low-voltage/power applications. However, the devices with smaller diameters of 75 and 45 nm show peculiar characteristics, such as a second rise of the drain current in output characteristics and a negative transconductance.

Effects of Interface Traps and Self-Heating on the Performance of GAA GaN Vertical Nanowire MOSFET

In the past couple of years, GaN-based vertical FETs have been explored to complement their potential logic applicability along with its well-known advantages in high-power and RF applications. In this article, the performances of short-channel gate-all-around (GAA) GaN vertical nanowire MOSFETs, fabricated for a possible low-voltage logic application, have been investigated via simulation, assuming the multilevel trapping effects at the gate interface and the self-heating effects. The simulation results reveal that shallow traps at the interface increase the OFF-state current, the subthreshold swing, and the drain-induced barrier lowering, while deep traps at the interface lower the ON-state current and cause the threshold voltage instability. When the gate voltage is higher than the flat-band voltage of the nanowire channel in the saturation region of operation, the mobility degradation, related to the self-heating, becomes significant due to the increased incorporation of the optical phonon scattering.

Low voltage operation of GaN vertical nanowire MOSFET

• GaN vertical nanowire MOSFET is fabricated by top-down approach. • Both threshold voltage and saturation voltage below 1 V are due to the small diameter and carrier concentration of channel. • GaN vertical nanowire MOSFET show small current collapse due to high gate controllability. • GaN vertical nanowire MOSFET is also promising for low voltage logic applications.

Low voltage operation of GaN vertical nanowire MOSFET

GaN gate-all-around (GAA) vertical nanowire MOSFET (VNWMOSFET) with channel length of 300 nm and diameter of 120 nm, the narrowest GaN-based vertical nanowire transistor ever achieved from the top-down approach, was fabricated by utilizing anisotropic side-wall wet etching in TMAH solution and photoresist etch-back process. The VNWMOSFET exhibited output characteristics with very low saturation drain voltage of less than 0.5 V, which is hardly observed from the wide bandgap-based devices. Simulation results indicated that the narrow diameter of the VNWMOSFET with relatively short channel length is responsible for the low voltage operation. The VNWMOSFET also demonstrated normally-off mode with threshold voltage (VTH) of 0.7 V, extremely low leakage current of ∼10−14 A, low drain-induced barrier lowering (DIBL) of 125 mV/V, and subthreshold swing (SS) of 66–122 mV/decade. The GaN GAA VNWMOSFET with narrow channel diameter investigated in this work would be promising for new low voltage logic application.

Sub-Thermal Subthreshold Characteristics in Top–Down InGaAs/InAs Heterojunction Vertical Nanowire Tunnel FETs

This letter demonstrates top-down InGaAs/InAs heterojunction vertical nanowire tunnel FETs with sub-thermal subthreshold characteristics over two orders of magnitude of current. A minimal subthreshold swing of 53 mV/decade at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</sub> = 0.3 V has been obtained at room temperature. An I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">60</sub> (defined as the highest current level where the subthreshold characteristics exhibit a transition from sub- to super-60 mV/decade behavior) of 4.3 nA/μm has been achieved at V s = 0.3 V. Compared with an earlier device generation, much reduced temperature dependence of the subthreshold characteristics is observed in this letter. The major difference between the two device generations is the drastically reduced interface trap density, evidenced by the improvement in the subthreshold swing of InGaAs vertical nanowire MOSFETs fabricated at the same time. This result suggests oxide-semiconductor interface trap-assisted tunnelling the main leakage mechanism in III-V TFETs fabricated by our process. The improvement in the interface quality has been enabled by improved gate oxide deposition and post-deposition treatment.

Source/Drain Asymmetry in InGaAs Vertical Nanowire MOSFETs

This paper demonstrates InGaAs vertical nanowire (VNW) MOSFETs fabricated via an improved top–down approach, the performance of which is comparable to that of the best bottom–up devices in terms of the balance between transport and electrostatics. These devices, when contrasted with an earlier generation fabricated by a similar technology, have enabled the first experimental study of source/drainasymmetry in InGaAs VNWMOSFETs. The transconductance differs significantly when swapping source and drain due to inherently different top and bottom contact electrical resistance. This also results in distinct asymmetry in the saturation behavior of the output characteristics. On the other hand, diameter nonuniformity along the nanowire (NW) length is responsible for asymmetry in the subthreshold characteristics. A uniform NW cross section, enabled by our improved InGaAs dry etch technology in the present devices, eliminates the asymmetry of the electrostatics, which was observed in our previous work.

비대칭 소스/드레인 수직형 나노와이어 MOSFET의 1T-DRAM 응용을 위한 메모리 윈도우 특성

비대칭 소스/드레인 수직형 나노와이어 MOSFET의 1T-DRAM 응용을 위한 메모리 윈도우 특성

Effect of source and drain asymmetry on hot carrier degradation in vertical nanowire MOSFETs

Effects of source and drain (S/D) asymmetry on hot carrier degradation in vertical nanowire MOSFETs have been investigated with different nanowire radiuses. The S/D asymmetry causes different degree of hot carrier degradations between forward and reverse stresses. The actual stress voltage applied to the channel as a result of parasitic resistance and gate to junction overlap length is attributed to the cause of the asymmetric degradation. The narrower nanowire also suffers from worse hot carrier effects due to current crowding and geometric effects.

Design of RF Properties for Vertical Nanowire MOSFETs

The RF performance of vertical nanowire metal-oxide-semiconductor field-effect transistors in realistic layouts has been calculated. The parasitic capacitances have been evaluated using full 3-D finite-element method calculations, combined with self-consistent Schrodinger-Poisson calculations for the intrinsic gate capacitances. It is shown that a performance comparable to planar FETs can be achieved in the vertical geometry by scaling the nanowire diameter and the wire-to-wire separation.