Vertical Interconnect Access Research Articles

Novel design and implementation of 3d packaged wideband bandpass filters

This study presents an innovative method for designing a 3D packaged wideband bandpass filter (BPF) by vertically integrating a high-pass filter (HPF) and a low-pass filter (LPF) using an air cavity and vertical interconnect accesses (VIAs). This integration enhances performance while significantly reducing system size. The fabricated BPF, constructed on multilayer substrates, achieves a passband from 2.175 to 4.2 GHz with less than 2.5 dB insertion loss and a return loss exceeding 10 dB. The design utilizes a partial substrate integrated suspended line (SISL) structure, enabling precise control over the equivalent dielectric constant and characteristic impedance to optimize insertion loss. The height of the air cavity, determined through theoretical analysis and S-parameter inversion, is critical for achieving optimal filter performance. The methodology allows for independent circuit designs on each layer, resulting in a 3D assembly. This refined approach makes it easier to produce compact bandpass and multi-band filters, simplifying circuit development and enabling scalable fabrication. This design is versatile across different frequency ranges, demonstrating significant practical and theoretical benefits.

Contact Hole Shrinkage: Simulation Study of Resist Flow Process and Its Application to Block Copolymers.

For vertical interconnect access (VIA) in three-dimensional (3D) structure chips, including those with high bandwidth memory (HBM), shrinking contact holes (C/Hs) using the resist flow process (RFP) represents the most promising technology for low-k1 (where CD=k1λ/NA,CD is the critical dimension, λ is wavelength, and NA is the numerical aperture). This method offers a way to reduce dimensions without additional complex process steps and is independent of optical technologies. However, most empirical models are heuristic methods and use linear regression to predict the critical dimension of the reflowed structure but do not account for intermediate shapes. In this research, the resist flow process (RFP) was modeled using the evolution method, the finite-element method, machine learning, and deep learning under various reflow conditions to imitate experimental results. Deep learning and machine learning have proven to be useful for physical optimization problems without analytical solutions, particularly for regression and classification tasks. In this application, the self-assembly of cylinder-forming block copolymers (BCPs), confined in prepatterns of the resist reflow process (RFP) to produce small contact hole (C/H) dimensions, was described using the self-consistent field theory (SCFT). This research paves the way for the shrink modeling of the enhanced resist reflow process (RFP) for random contact holes (C/Hs) and the production of smaller contact holes.

High-Speed Signal Optimization at Differential VIAs in Multilayer Printed Circuit Boards

The number of Printed Circuit Board (PCB) layers is continually increasing with the increase in data transmission rates, and the Signal Integrity (SI) of high-speed digital systems cannot be ignored. Introducing Vertical Interconnect Accesses (VIAs) in PCBs can realize the electrical connection between the top layer and the inner layers, however, VIAs represent one of the most important reasons for discontinuity between the PCBs and package. In this paper, a new optimization scheme for a differential VIA stub is proposed, with 3D full-wave numerical simulation used for modeling and simulation. Results show that this scheme optimizes the return loss and insertion loss while making the signal eye diagram more ideal, which can improve the transmission effect of high-speed signals.

Highly Stable Liquid Metal Conductors with Superior Electrical Stability and Tough Interface Bonding for Stretchable Electronics.

Ga-based liquid metal stretchable conductors have recently gained interest in flexible electronic devices such as electrodes, antennas, and sensors. It is essential to maintain electrical stability under strain or cyclic strain for reliable data acquisition and exhibit tough interfacial bonding between liquid metal and polymers to prevent performance loss and device failure. Herein, a highly stable conductor with superior electrical stability and tough interface bonding is introduced by casting curable polymers and a peeling-activated process from liquid metal particles. Based on the compensating effect of liquid metal, similar to the recharge relationship of water between rivers and lakes in nature, the conductor is not only strain-insensitive (ΔR/R0 < 10% for 100% strain) but also immune to cyclic deformation (ΔR/R0 < 7% with 5000 stretching cycles at 50% strain). Embedding liquid metal within the elastomer to create stretchable conductors effectively improves interfacial adhesion properties (the fluid-solid interfacial adhesion force increases from 0.48 to 0.62 mN/mm2). The constructed tough interface could even withstand sonication treatment. Finally, by combining strategies in material design and fabrication, an integrated array composed of vertical interconnect access and robust electrodes is fabricated, which simultaneously holds tough interfacial bonding with the upper and lower layers.

Multilayer Flexible SU8-Gold Microelectrode Arrays for Wearable Bioelectronics

Wearable health trackers for vital signs monitoring are becoming ever more important especially due to the global coronavirus pandemic (COVID-19) caused by the SARS‑CoV‑2 virus which severely affect the respiratory system and can cause cardiac manifestations. Particularly, wearable solutions which can seamlessly monitor heart activity are critical to facilitate personal preventive and remote healthcare, as well as to allow early diagnosis of cardiac dysfunctions. A fundamental enabler of wearable bioelectronics is the sensing bioelectrode which is used to record surface biopotentials. While a plethora of attempts have been reported to realize skin-conformal dry electrodes and electronic skin patches, oftentimes a very critical aspect of the electrode i.e., the actual electrical interfacing of the wearable electrode to readout circuits without disturbing the skin-electrode contact, is overlooked. To address this issue, this paper reports a unique tri-layer, polymer-metal-polymer skin-conformal microelectrode design with sidewall metal coating to achieve vertical interconnect accesses (VIAs) and realize contact pads for external interfacing. The novel and optimized process flow reported herein allows repeatable fabrication of flexible electrodes in arrayed format with yields exceeding 90%. Functionality of the microfabricated electrodes were demonstrated by successful acquisition of the electrocardiogram in lead-I configuration with clear detection of the P-QRS-T complex.

Ultrahigh Strain-Insensitive Integrated Hybrid Electronics Using Highly Stretchable Bilayer Liquid Metal Based Conductor.

Human-interfaced electronic systems require strain-resilient circuits. However, present integrated stretchable electronics easily suffer from electrical deterioration and face challenges in forming robust multilayered soft-rigid hybrid configurations. Here, a bilayer liquid-solid conductor (b-LSC) with amphiphilic properties is introduced to reliably interface with both rigid electronics and elastomeric substrates. The top liquid metal can self-solder its interface with rigid electronics at a resistance 30% lower than the traditional tin-soldered rigid interface. The bottom polar composite comprising liquid metal particles and polymers can not only reliably interface with elastomers but also help the b-LSC heal after breakage. The b-LSC can be scalably fabricated by printing and subsequent peeling strategies, showing ultra-high strain-insensitive conductivity (maximum 22532Scm-1 ), extreme stretchability (2260%), and negligible resistance change under ultra-high strain (0.34 times increase under 1000% strain). It can act as stretchable vertical interconnect access for connecting multilayered layouts and can be scalably and universally fabricated on various substrates with a resolution of ≈200µm. It is demonstrated that it can construct stretchable sensor arrays, multi-layered stretchable displays, highly integrated haptic user-interactive optoelectric E-skins, visualized heaters, robot touch sensing systems, and wireless powering for wearable electronics.

Solvent-Assisted Filling of Liquid Metal and Its Selective Dewetting for the Multilayered 3D Interconnect in Stretchable Electronics.

As stretchable electronics are rapidly developing and becoming complex, the requirement for stretchable, multilayered, and large-area printed circuit boards (PCBs) is emerging. This demands a stretchable electrode and its vertical interconnect access (via) for 3-dimensional (3D) connectivity between layers. Here, we demonstrate solvent-assisted liquid metal (LM) filling into the submicrometer channel (∼400 nm), including via-hole filling and selective dewetting of LM. We provide the theoretical background of solvent-assisted LM filling and selective dewetting and reveal the osmotic pressure arising from anomalous mass transport phenomena, case II diffusion, which drives negative pressure, the spontaneous pulling of LM into the open channel. Also, we suggest design criteria for the geometry and dimension of LM interconnects to obtain structural stability without dewetting, based on the theoretical and computational background. We demonstrate a simple stretchable near-field communication (NFC) device including transferred micrometer-size light-emitting diodes (LEDs) with only 230 μm to the stretchable liquid metal PCB, without any soldering process. The device operates stably under repetitive stretching and releasing (∼50% uniaxial strain) due to the stable connection through the LM via between the upper and lower layers. Finally, we propose a concept for modular-type stretchable electronics, based on the cohesive liquid nature of LM. As a building block, the functional module can be easily removed from a mainframe, and replaced by another functional module, to suit user demand.

Enhanced throughput and clean laser drilling with a sacrificial polymer layer

Laser micromachining is the chosen method for vertical interconnect access point (VIA) formation in flex PCB layers. Even so, this method suffers from several inherent physical issues as a result of the intense localized heating causing strong Marangoni convection and the buildup of recast along the VIA upper crater walls while also scattered particle debris and oxidation of copper across the surface. The mitigation of the height and radius of this recast layer is critical for the following build-up process and device functionality and reliability. This is currently a major technology inhibitor to the adoption of flex PCBs for high-power electronics. In this study, we present experimental results showing the use of engineered sacrificial layers that coat the surface of the flex PCB substrate during the laser micromachining process. Optimization of this engineered sacrificial layer resulted in a major improvement in recast quality and debris control as well as reducing the oxide formation while increasing the laser drilling efficiency, attributable to increased surface pressure on the substrate. In this paper, we describe the methods and materials used in the development of sacrificial layers and show the positive impact it achieves on improving and modifying the plasma characteristics throughout the overall laser drilling process.

Self‐Aligning Metallic Vertical Interconnect Access Formation through Microlensing Gas Phase Electrodeposition controlling Airgap and Morphology

AbstractThis publication reports self‐aligning metallic via microlensing gas phase electrodeposition formation. Key operational parameters to fabricate vertical ruthenium and rhodium interconnects (via) with a diameter of 100 nm are discussed. Moreover, airgaps are implemented during the deposition process, which utilizes spark discharge to generate a flux of charged nanoparticles. An inert gas flow transports the nanoparticles through a reactor chamber close to the target substrate. The substrate uses a pre‐patterned resist with openings to a silicon/silicon dioxide/metal stack to direct the deposition of the nanoparticles to form localized self‐aligning vertical interconnects. Five process parameters were identified, which impact the morphology and conductance of the resulting interconnects: spark discharge power, gas flow rate, microlens via dimensions, substrate surface potential, and in situ flash lamp power. This parameter set enables a controlled adjustment of the via interconnect morphology and its minimum feature size. Gas flow rate in combination with spark discharge power contribute significantly to the morphology of the interconnect. Spark power and microlens via dimensions have the largest influence on the surface potential of the insulating resist cover, which enables a localized microlensing gas phase electrodeposition of a via with a controlled ratio between conducting diameter and airgap.

Sweat analysis with a wearable sensing platform based on laser-induced graphene.

The scientific community has shown increasing interest in laser scribing for the direct fabrication of conductive graphene-based tracks on different substrates. This can enable novel routes for the noninvasive analysis of biofluids (such as sweat or other noninvasive matrices), whose results can provide the rapid evaluation of a person's health status. Here, we present a wearable sensing platform based on laser induced graphene (LIG) porous electrodes scribed on a flexible polyimide sheet, which samples sweat through a paper sampler. The device is fully laser manufactured and features a two layer design with LIG-based vertical interconnect accesses. A detailed characterization of the LIG electrodes including pore size, surface groups, surface area in comparison to electroactive surface area, and the reduction behavior of different LIG types was performed. The bare LIG electrodes can detect the electrochemical oxidation of both uric acid and tyrosine. Further modification of the surface of the LIG working electrode with an indoaniline derivative [4-((4-aminophenyl)imino)-2,6-dimethoxycyclohexa-2,5-dien-1-one] enables the voltammetric measurement of pH with an almost ideal sensitivity and without interference from other analytes. Finally, electrochemical impedance spectroscopy was used to measure the concentrations of ions through the analysis of the sweat impedance. The device was successfully tested in a real case scenario, worn on the skin during a sports session. In vitro tests proved the non-cytotoxic effect of the device on the A549 cell line.

Computational analysis of copper electrodeposition into a porous preform

Electroplating of metals into a porous preform with conductive walls is relevant in the fabrication of structural composites, fuel cells and batteries, and microelectronics. Electrodeposition process parameters, such as direct current or pulsed current, electric potential, and electrolyte concentration, as well as preform geometry, have important implications in the process outcomes including the filling process and the percentage of the infiltrated volume. Although electroplating into a vertical interconnect access (with nonconductive walls) for microelectronic applications has been extensively studied, the "flow-through" electroplating into a channel geometry with conducive walls has not been previously investigated. Here, copper infiltration into a such channel has been investigated using computational analysis for the first time. The effects of the inlet flow velocity, potential, electrolyte concentration, and microchannel geometry are systematically studied to quantify their influence on the electrodeposition rate, uniformity of the deposition front, and the infiltrated area within the channel. Computational results revealed that the unfilled area can be reduced to lower than 1% with a low applied potential, a high electrolyte concentration, and no inflow velocity. The results can be used to guide experiments involving electroplating metals into porous preforms toward reliable and reproducible manufacturing processes.

An Optimization Framework for the Design of High-Speed PCB VIAs

Signal integrity represents a key issue in all modern electronic systems, which are strongly dominated by the extreme component density usually employed on PCBs and the associated increase in the interconnection density. The use of multi-layer structures with microstrips connected by various types of Vertical Interconnect Accesses (VIAs) calls for design strategies that reduce the impedance mismatch and signal attenuation. The paper proposes a thorough analysis of the effects associated with the VIA geometry and presents a parametric evaluation of them. The obtained results represent the starting point for a possible design procedure that manages the geometric aspects of differential VIAs, aiming to optimize their electrical performance while reducing their occupation of PCB area. The optimization technique considers a differential VIA as a four-port circuit whose characteristics are evaluated with suitable Figures of Merit (FoMs), thus striving for an optimal design obtained with closed-loop iterations. The analysis is performed in both the time (TDR: Time-Domain Reflectometry) and frequency domains (S and Z parameters), thus allowing a dramatic reduction in the number of cases to be analyzed. The procedure is thoroughly described and validated using simulation results.

Direct Fabrication of VIA Interconnects by Electrohydrodynamic Printing for Multi‐Layer 3D Flexible and Stretchable Electronics

AbstractMulti‐layer electrical interconnects are critical for the development of integrated soft wearable electronic systems, in which functional devices from different layers need to be connected together by vertical interconnects. In this work, electrohydrodynamic (EHD) printing technology is studied to achieve multi‐layer flexible and stretchable electronics by direct printing vertical interconnects as vertical interconnect accesses (VIAs) using a low‐melting‐point metal alloy. The EHD printed metallic vertical interconnection represents a promising way for the direct fabrication of multilayer integrated electronics with metallic conductivity and excellent flexibility and stretchability. By controlling the printing conditions, vertical interconnects that can bridge different heights can be fabricated. To achieve reliable VIA connections under bending and stretching conditions, an epoxy protective structure is printed around the VIA interconnects to form a core‐shell structure. A stable electrical response is achieved under hundreds of bending cycles and during stretching/releasing cycles in a large range of tensile strain (0–40%) for the printed conductors with VIA interconnects. A few multi‐layer devices, including a multiple layer heater, and a pressure‐based touch panel are fabricated to demonstrate the capability of the EHD printing for the direct fabrication of vertical metallic VIA interconnects for flexible and stretchable devices.

Superconducting Contacts to a Monolayer Semiconductor.

We demonstrate superconducting vertical interconnect access (VIA) contacts to a monolayer of molybdenum disulfide (MoS2), a layered semiconductor with highly relevant electronic and optical properties. As a contact material we use MoRe, a superconductor with a high critical magnetic field and high critical temperature. The electron transport is mostly dominated by a single superconductor/normal conductor junction with a clear superconductor gap. In addition, we find MoS2 regions that are strongly coupled to the superconductor, resulting in resonant Andreev tunneling and junction-dependent gap characteristics, suggesting a superconducting proximity effect. Magnetoresistance measurements show that the bandstructure and the high intrinsic carrier mobility remain intact in the bulk of the MoS2. This type of VIA contact is applicable to a large variety of layered materials and superconducting contacts, opening up a path to monolayer semiconductors as a platform for superconducting hybrid devices.

Methods for latent image simulations in photolithography with a polychromatic light attenuation equation for fabricating VIAs in 2.5D and 3D advanced packaging architectures

As demand accelerates for multifunctional devices with a small footprint and minimal power consumption, 2.5D and 3D advanced packaging architectures have emerged as an essential solution that use through-substrate vias (TSVs) as vertical interconnects. Vertical stacking enables chip packages with increased functionality, enhanced design versatility, minimal power loss, reduced footprint and high bandwidth. Unlocking the potential of photolithography for vertical interconnect access (VIA) fabrication requires fast and accurate predictive modeling of diffraction effects and resist film photochemistry. This procedure is especially challenging for broad-spectrum exposure systems that use, for example, Hg bulbs with g-, h-, and i-line UV radiation. In this paper, we present new methods and equations for VIA latent image determination in photolithography that are suitable for broad-spectrum exposure and negate the need for complex and time-consuming in situ metrology. Our technique is accurate, converges quickly on the average modern PC and could be readily integrated into photolithography simulation software. We derive a polychromatic light attenuation equation from the Beer-Lambert law, which can be used in a critical exposure dose model to determine the photochemical reaction state. We integrate this equation with an exact scalar diffraction formula to produce a succinct equation comprising a complete coupling between light propagation phenomena and photochemical behavior. We then perform a comparative study between 2D/3D photoresist latent image simulation geometries and directly corresponding experimental data, which demonstrates a highly positive correlation. We anticipate that this technique will be a valuable asset to photolithography, micro- and nano-optical systems and advanced packaging/system integration with applications in technology domains ranging from space to automotive to the Internet of Things (IoT).

Vertical Integration of Passive Microwave Components Using Functional Via Structures in LTCC Multilayer Substrates

A recently developed concept for designing passive microwave components using functional vertical interconnect accesses (vias) for vertical integration in printed circuit boards (PCBs) is extended and transferred to the low temperature cofired ceramic (LTCC) technology. Given the changed material properties and new technology constraints, it is shown how and to what extent the controlled vertical interconnect accesses (via) structures can behave as quasi-transmission lines, thus allowing for another degree of freedom in component design. To demonstrate the validity and utility of functional vias, several novel microwave components are proposed and subsequently analyzed including vertically integrated 2- and 3-way Wilkinson power dividers, as well as vertically integrated 90° and 180° hybrid couplers. Prototypes for the 2-way and 3-way power dividers were manufactured on an LTCC multilayer substrate. Both measurement and full-wave simulation results are in excellent agreement and thus provide a proof of the concept.

Pneumatic Enabled Vertical Interconnect Access of Liquid Alloy Circuits toward Highly Integrated Stretchable Electronics

AbstractMultilayer circuits, particularly in stretchable electronics, are always considered as an effective way to integrate diverse components and modules for advanced/powerful functions required in the potential applications or complex scenarios. As a desirable soft conductor, liquid alloy circuits exhibit super compliance and stretchability. However, the lacking of reliable ways to fabricate multilayer circuits like other stretchable electronics, the advantage of liquid alloy stretchable electronics is far away well exploited, especially from the perspectives of application developments. Here, based on the unique features of rapid oxidation and fluidity from liquid alloy, a facile method is presented to achieve multilayer circuits connection with vertical interconnect accesses enabled by pneumatic blowing and surface topography tuning. This approach provides a new way to achieve high integration of liquid alloy based stretchable electronics, for example, a double‐layer soft LED array, a conformal six‐layer wireless charging, and a wireless communicated wearable device for temperature and humidity real‐time monitoring. Furthermore, compatible with conventional industry process, it may open a new window for making advanced or powerful liquid alloy stretchable electronics for various applications in complex scenarios.

Additive manufacturing of copper vertical interconnect accesses by laser processing

This paper introduces a new manufacturing process for vertical interconnect accesses (VIA). In contrast to industrially established VIA metallization technologies, the presented approach takes place without any chemical plating by combining copper ink and epoxy insulator coating with CO 2 laser processing for VIA drilling and copper ink sintering. The minimum VIA resistances are less than 50 mΩ, fitting the theoretically calculated value. A laboratory application scenario testing a 10 × 10 contact pad array with a pitch of 800 µm successfully demonstrates routing across five printed metallization layers, including 128 blind and 112 buried VIA.

Introducing Functional Via Structures to Low Temperature Cofired Ceramics: How to Optimize Reliably and Efficiently

Low temperature cofired ceramics (LTCCs) refer to a mature technology with low-loss dielectric materials, high quality conductors, and high dimensional accuracy. This class of ceramics-based substrates is a popular choice for integration of a variety of electronics with active and passive components in both single- and multilayered environments. Vertical interconnect accesses (vias) are widely used in LTCC and elsewhere for signal routing as well as power and ground supply within the stack-up. Since vias represent discontinuities in the signal path, they introduce parasitic elements that inevitably degrade the electrical performance. This work intends to delineate two distinct, straightforward, and efficient ways to estimate as well as control via impedance and phase delay. The usability of vias in LTCC is extended through the concept of functional via structures, which is based on the generalization of vias as quasi-coaxial lines that behave similarly to real transmission lines. The advantage of the proposed concept is highlighted by deploying vias for three-dimensional (3-D) integration of power dividers, and improving the signal integrity (SI) and power integrity (PI) of via arrays in LTCC multilayered substrates.

Reflective Switchable Polarization Rotator Based on Metasurface With PIN Diodes

A planar metasurface that rotates the polarization of reflected signals by 90° is presented in this article. The surface also permits the relative phase of the rotated, reflected signal to be controlled. The metasurface rotator uses a square printed patch element mounted above a conducting ground plane. The addition of PIN diode controlled vertical interconnect access (VIA) at the corners of each square patch provides the ability to modify the scattering properties of the surface. In particular, the surface can be programed to shift the phase of the rotated waveform by ±90°. The polarization rotator was manufactured, measured, and compared against numerical simulations, and the maximum measured bandwidth was 25% (4.8-6.2 GHz) for co-polarized attenuation of 10 dB. The proposed surface can be adopted for practical applications, such as circularly polarized antennas.