An Optimization Framework for the Design of High-Speed PCB VIAs

Gianfranco Avitabile,Lorenzo Forni,Antonello Florio,Alessandro Pali,Vito Leonardo Gallo

doi:10.3390/electronics11030475

Gianfranco Avitabile, Lorenzo Forni + Show 3 more

Open Access

https://doi.org/10.3390/electronics11030475

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Journal: Electronics	Publication Date: Feb 6, 2022
Citations: 1	License type: CC BY 4.0

Affiliation: Polytechnic University of Bari

Abstract

Signal integrity represents a key issue in all modern electronic systems, which are strongly dominated by the extreme component density usually employed on PCBs and the associated increase in the interconnection density. The use of multi-layer structures with microstrips connected by various types of Vertical Interconnect Accesses (VIAs) calls for design strategies that reduce the impedance mismatch and signal attenuation. The paper proposes a thorough analysis of the effects associated with the VIA geometry and presents a parametric evaluation of them. The obtained results represent the starting point for a possible design procedure that manages the geometric aspects of differential VIAs, aiming to optimize their electrical performance while reducing their occupation of PCB area. The optimization technique considers a differential VIA as a four-port circuit whose characteristics are evaluated with suitable Figures of Merit (FoMs), thus striving for an optimal design obtained with closed-loop iterations. The analysis is performed in both the time (TDR: Time-Domain Reflectometry) and frequency domains (S and Z parameters), thus allowing a dramatic reduction in the number of cases to be analyzed. The procedure is thoroughly described and validated using simulation results.

Highlights

Introduction andState-of-the ArtAcademic Editor: Antonio OrlandiIn recent decades, technological advances have forced a qualitative leap in the design of Printed Circuit Boards (PCBs) given the new requirements in terms of size reduction, increased operating speed, and component density
The optimization technique considers a differential Vertical Interconnect Accesses (VIAs) as a four-port circuit whose characteristics are evaluated with suitable Figures of Merit (FoMs), striving for an optimal design obtained with closed-loop iterations
Technological advances have forced a qualitative leap in the design of Printed Circuit Boards (PCBs) given the new requirements in terms of size reduction, increased operating speed, and component density

Summary

Introduction

Technological advances have forced a qualitative leap in the design of Printed Circuit Boards (PCBs) given the new requirements in terms of size reduction, increased operating speed, and component density To meet these needs, PCB design evolved towards multi-layer structures with vertical interconnections between the different levels [1,2] with so-called VIAs, whose tight connection with technological progress was clearly described by [3]. Signal Integrity (SI) issues require a careful evaluation of the performance of VIA interconnections [4] Their optimization usually implies the correction of the geometric design with the aim of the minimization of such issues. Mallikarjun et al [10]

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Results

Conclusion