Vertical Field Effect Transistor Research Articles

Vertical 3D diamond field effect transistors with nanoscale gate-all-around

Recent studies have shown that diamond field effect transistors (FETs) have great potential in high-power and high-frequency electronics, exhibiting the maximum leakage current of 1.35 A·mm−1 and the breakdown voltage of 2 kV. However, there is still a lack of preliminary exploration on diamond FETs with a three-dimensional (3D) architecture, which has been evidenced as a promising approach to increase device performance and density for silicon transistors. In this paper, we present a systematic investigation of 3D vertical gate-all-around (GAA) diamond transistors, combined with numerical simulation, device fabrication and characterization of device performance. The p-type conductivity of the diamond channel in a transistor is obtained by Boron-ion implantation. Our numberical simulations address the close correlation of transfer characteristics of the 3D vertical GAA diamond transistors with the ion implanted impurities. In the device fabrication, we introduce the focused ion and electron beam technology for the electrode interconnections in the 3D devices. Finally, we demonstrate that the 3D vertical GAA diamond transistor exhibits the on-off ratio of 2.5 × 103, subthreshold swing of 334.3 mV·dec−1, and threshold voltage of 0.64 V. And the temperature dependence of transfer characteristics of the 3D devices indicates that 3D vertical GAA diamond transistors have potential application prospects in extreme environments such as high temperature.

An analytical drain current model of Germanium source vertical tunnel field effect transistor

This paper presents an analytical modeling of the drain current for a Germanium source vertical tunnel field effect transistor. Both one dimensional (1D) and two dimensional (2D) Poisson's equation are used for solving the potential distribution as the device structure possess both vertical and lateral band-to-band tunneling components. The 2D band-to-band tunneling model is employed for solving the lateral tunneling while the 1D band-to-band tunneling model is implemented on solving the vertical tunneling which consist of the source region and the overlap channel region. The length of the maximum and minimum tunneling widths are calculated by measuring the distance from the edge of the valence band to conduction band of the energy band profile. Kane's band-to-band tunneling generation rate is used to model the drain current by superimposing two current components. In addition, the impact of bandgap narrowing as well as quantum correction on the drain current are also factored into the model. The analytical models are checked and matched against the results obtained from the TCAD simulations to ensure its accuracy.

Extended Gate to source overlap Heterojunction Vertical TFET: Design, analysis, and optimization with process parameter variations

This report highlights the simulated results of Extended gate to source overlap Heterojunction Vertical Tunnel field effect transistor (EGH-VTFET) for low-power and high-performance applications. To boost the DC as well as Analog/RF performance parameters, a novel heterojunction double gate Vertical TFET structure is reported by utilizing germanium as a source material and Si as a channel and drain material. Further, optimization of performance parameters is carried out on the basis of process parameter variations. In addition, a thorough analysis of both DC and Analog/RF performance is carried out for proposed EGH-VTFET device with optimization and without optimization. A wide range of figure of merits(FOM) such as on-current(Ion), current ratio (Ion/Ioff), total gate capacitance(Cgg), transconductance(gm), output conductance(gds), transconductance to current ratio(gm/Id), cut-off frequency(fT) and intrinsic gain(Av) have been analysed.

Detection of SARS-CoV-2 using dielectric modulated TFET-based biosensor.

Attributable to the rapid increase in human infection of Coronavirus disease 2019 (COVID-19) caused by severe acute respiratory syndrome coronavirus-2 (SARS-CoV-2), the World Health Organization (WHO) has declared this disease outbreak as a pandemic. This outbreak can be tackled to some extent through proper management and early diagnosis. This work reports a biosensor based on vertical tunnel field-effect transistor (VTFET) developed for the detection of SARS-CoV-2 from the clinical samples through the analysis of its spike, envelope, and DNA proteins. Investigation of the sensitivity of the proposed sensor has been done by calculating the shift in drain current. The dielectric constant equivalent of the virus proteins is used to represent the hybridized biomolecules within the nanogaps. The sensitivity of this proposed sensor is found to be significantly high (order of 106) showing the viability of the device to be a superior sensor. Furthermore, the sensitivity analysis concerning DNA charge density is also performed. The effect of DNA charge density variation on the threshold voltage (Vth) and sensitivity have also been studied in this work. The proposed sensor is also investigated for its noise performance and observed the sensitivity with and without the effect of interface trap charges. Finally, the proposed sensor is benchmarked against the sensitivity of various FET-based biosensors already published earlier.

SnO/β-Ga2O3 heterojunction field-effect transistors and vertical p–n diodes

In this work, we report on the realization of SnO/β-Ga2O3 heterojunction vertical diodes and lateral field-effect transistors for power electronic applications. The p-type semiconductor SnO is grown by plasma-assisted molecular beam epitaxy on n-type (100) β-Ga2O3 with donor concentrations of 3 × 1017 cm−3 for the diode devices and 8.1 × 1017 cm−3 for the field-effect transistors. The deposited films show a predominant SnO (001) phase featuring a hole concentration and a mobility of 7.2 × 1018 cm−3 and 1.5 cm2/V s, respectively. The subsequent electrical characterization of the heterojunction diodes and field-effect transistors show stable switching properties with on/off current ratios >106 and specific on-resistances below 4 mΩ cm2. Furthermore, breakdown measurements in air of the non-field-plated heterojunction transistor with a gate-to-drain distance of 4 μm yield a breakdown voltage of 750 V, which equals an average breakdown strength of nearly 1.9 MV/cm. The resulting power figure of merit is calculated to 178 MW/cm2 demonstrating state-of-the-art properties. This emphasizes the high potential of this heterojunction approach.

Interfacial charge analysis and temperature sensitivity of germanium source vertical tunnel FET with delta-doped layer

The influence of interface trap charges (ITCs) and reliability of the Germanium source vertical tunnel field effect transistor with delta-doped layer (GSDD vTFET) is investigated in this paper. The analysis is carried out on the GSDD vTFET by evaluating the analog/RF performances under the consideration of donor and acceptor ITCs and temperature variations. The presence of interface trap charges at the silicon channel/gate oxide interface changes the flat-band voltage, affecting the analog and RF performances of the GSDD vTFET. The study is carried out at distinctive donor and acceptor interface trap charges. The findings indicate that as the interface trap charge densities increases, the device's output changes drastically. The off-state current of the GSDD vTFET deteriorates significantly from an order of 10−14 A to 10−8 A in the presence of positive ITC of 1012/cm2. The temperature variations over a wide range shows that OFF-state current as well as subthreshold region gets deteriorated due to dominance of Shockley–Read–Hall effect and the superthreshold region is less affected owing to dependence of band-to-band tunneling. The results reveal that when the temperature is raised from 200 K to 400 K, the ION/IOFF current ratio degrades tremendously from ~1014 to ~108 in the existence of donor ITC. It is also observed that the GSDD vTFET is less susceptible to acceptor interface trap charge in comparison with donor ITC in a temperature sensitive environment. Quantum correction (QC) of GSDD vTFET with ITC shows the same type of variations as the condition without considering QC.

Correction to: A TCAD Approach to Analyze the Performance of Dual Gate Dielectric Modulated Vertical Tunnel Field Effect Transistor Based Biosensor

Correction to: A TCAD Approach to Analyze the Performance of Dual Gate Dielectric Modulated Vertical Tunnel Field Effect Transistor Based Biosensor

Vertical Cladding Layer-Based Doping-Less Tunneling Field Effect Transistor: A Novel Low-Power High-Performance Device

This article introduces a novel vertical doping-less tunnel field-effect transistor (TFET), in which instead of using metal to induce charge plasma in the source region, cladding layer is utilized to engineer the energy bands in this region. The fabrication process flow of this highly scalable TFET is presented in detail. We employ a calibrated numerical simulator to study the switching and analog/RF performance of the proposed device. Moreover, the impact of different structural parameters and parasitic phenomena, such as interface trap charges and quantum confinement, on the device performance are investigated. According to the obtained results, our transistor exhibits desirable analog and digital performance including <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{ \mathrm{\scriptscriptstyle ON}} = 30.02 ~\mu \text{A}/\mu \text{m}$ </tex-math></inline-formula> , <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ </tex-math></inline-formula> ratio of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.57\times10$ </tex-math></inline-formula> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sup> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${f}_{T} = 89.31$ </tex-math></inline-formula> GHz.

Vertical organic phototransistors realized by femtosecond laser ablation patterned metal/insulator bilayer source electrodes: Performance and numerical modeling

Compared with their conventional lateral counter parts, vertical organic phototransistors (VOPTs) have the advantage of fast response speed due to short channel lengths, and may find wide applications in the field of high speed photo detection. By operation of VOPTs, the source electrode plays the vital role. We report on fabrication, characterization and analysis of VOPTs with pulsed laser ablation patterned Al/LiF bilayer source electrode. A maximal photoresponsivity of 760 mA/W, external quantum efficiency ( EQE ) of 145%, specific detectivity of 1.6 × 10 11 Jones were obtained for un-optimized devices. For describing the output characteristics of the devices, a rough numerical model was developed by combining the theory of thermionic emission at metal/organic interface and space charge limited current conduction. • We innovatively achieved the manufacture of vertical channel field-effect transistors by using a porous metal/insulator bilayer source electrode. • We patterned the porous electrode by femtosecond laser ablation. • We proposed a phenomenological device model to getting quantitative insight into the working mechanism of VOPTs. • The un-optimized device in this work showed a maximal photoresponsivity of 760 mA/W, EQE of 145%, specific detectivity of 1.6 × 10 11 Jones.

Influence of Injection Barrier on Vertical Organic Field Effect Transistors

Organic field-effect transistors (OFETs) have shown great potential for applications that require low temperature deposition on large and flexible substrates. To increase their performance, in particular a high transconductance and transit frequency, the transistor channel length has to be scaled into the submicrometer regime, which can be easily achieved in vertical organic field effect transistors (VOFETs). However, despite high performance observed in VOFETs, these transistors usually suffer from short channel effects like weak saturation of the drain current and direct source-drain leakage resulting in large off currents. Here, we study the influence of the injection barrier at the source electrode on the OFF currents, on/off ratio, and transconductance of vertical OFETs. We use two semiconducting materials, 2,6-diphenyl anthracene (DPA), and C60 to vary the injection barrier at the source electrode and are able to show that increasing the Schottky barrier at the source electrode can decrease the direct source/drain leakage by 3 orders of magnitude. However, the increased injection barrier at the source electrode comes at the expense of an increased contact resistance, which in turn will decrease its transconductance and transit frequency. With the help of a 2D drift-diffusion simulation we show that the trade-off between low off currents and high transconductance is inherent to the current VOFET device setup and that new approaches have to be found to design VOFETs that combine good switching properties with high performance.

A TCAD Approach to Analyze the Performance of Dual Gate Dielectric Modulated Vertical Tunnel Field Effect Transistor Based Biosensor

A TCAD Approach to Analyze the Performance of Dual Gate Dielectric Modulated Vertical Tunnel Field Effect Transistor Based Biosensor

On the Current Saturation of Vertical Transistors With Conductive Network Electrodes

Vertical field effect transistors (VFETs) based on conductive network electrodes feature high current density and compatibility in printing processes. Here, the device structures of VFETs are designed and optimized toward good current saturation and a better ON–OFF ratio. Among the three different structures, a simple structure stands out as the best: a semiconducting layer is inserted below the source electrode to increase the injected area of carriers and to enhance L-type channels (the channels along the semiconductor–dielectric interface and then to the drain), whereas an insulating layer is added on the top and two sides of the source electrode to generate a depletion region and to suppress I-type channels (the channels from the top of the source to the drain). The introduction of moderate Schottky barriers to the source electrodes further benefits the current saturation and gate tuning. The 2D-technology computer-aided design (TCAD) simulations are performed to analyze the physical mechanisms by quantifying the distribution of potentials, carrier concentrations, and current densities. The simulated current–voltage relations show a differential output resistance over 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sup> <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Omega \cdot $ </tex-math></inline-formula> cm and an ON–OFF ratio over 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sup> , indicating that the problems of current saturation and the ON–OFF ratio in short-channel VFETs have been theoretically solved to some extent.

Progressive p-channel vertical transistors fabricated using electrodeposited copper oxide designed with grain boundary tunability.

A strategically designed electrodeposition method is proposed for the coating of p-type copper(i) oxide (Cu2O) channels for oxide thin film transistors. To date, conventional p-type oxide semiconductors have revealed a poor mobility and stability and this has obstructed the development of all oxide based logic devices. Furthermore, previous studies on p-type oxide transistors have been limited by the use of a typical planar type configuration. Our Cu2O electrodeposition method designed by incorporating Sb element promotes vertical alignment of the grain boundaries (GBs) and it perfectly coincides with the charge transport direction from the source to the drain in the vertical field effect transistors. These vertically aligned GBs are bundle type GBs and are likely to be ideal for vertical transistors with supreme electrical performances owing to the structurally suppressed grain boundary charge scattering. This alignment of the GBs in the electrodeposited Sb doped Cu2O (Sb:Cu2O) also demonstrates a superior vertical taper profile with conventional wet chemical etching owing to the extremely preferential etching rate along the GBs. Surprisingly, the sidewall formation, with a smooth and steep morphology causes the formation of abrupt and non-defective gate insulator/channel interfaces for superior spacer-free vertical transistors. Consequently, the Cu2O vertical field effect transistors exhibit extraordinary transistor performances of Vth = 0.4 V, μFE = 8 cm2 V-1 s-1, subthreshold swing = 0.24 V dec-1, on/off current ratio = 2 × 108 and qualified electrical and long-term stability characteristics under various environments. To the best of our knowledge, this is the first reported study on an electrodeposited method to design troublesome p-type oxide Cu2O as novel vertical transistors. Finally, power efficient logic inverter circuits with unprecedented performances, such as good noise margins, remarkable gain values of 15.6 (2 VDD) and 62.7 (5 VDD), and high frequency operation up to 10 kHz, are demonstrated using these p-type Cu2O transistors by interconnecting n-type IGZO transistors.

Zero power infrared sensing in 2D/3D-assembled heterogeneous graphene/In/InSe/Au.

Low- or self-powered infrared sensors can be used in a broad range of applications, including networking mobile edge devices and image recognition for autonomous driving technology. Here, we show state-of-the-art self-powered near-infrared (NIR) sensors using graphene/In/InSe/Au as a photoactive region. The self-powered NIR sensors show outstanding performance, achieving a photoresponsivity of ∼8.5 A W-1 and a detectivity of ∼1012 Jones at 850 nm light. Multiple self-powered InSe photodetectors with different device structures and contacts were systematically investigated. In particular, the asymmetrically assembled graphene/In/InSe/Au vertical heterostructure offers a high built-in field, which gives rise to efficient electron-hole pair separation and transit time that is shorter than the photocarrier lifetime. The built-in potential across the InSe was estimated using the Schottky barrier height at each metal contact with InSe, obtained using density functional theory calculations. We also demonstrate InSe vertical field-effect transistors and provide an out-of-plane carrier mobility of InSe. Using the out-of-plane mobility and structural parameters of each device, the built-in field, drift velocity, and corresponding transit time are estimated.

A Sub-1 V, Electrolyte-Gated Vertical Field Effect Transistor Based on ZnO/AgNW Schottky Contact

Few works on solution-processed zinc oxide vertical transistors and electrolyte-gated transistors have shown the merits of both architectures. Here, we present an electrolyte-gated vertical field-effect transistor (EGVFET) based on a spray-deposited zinc oxide/silver nanowire (ZnO/AgNW) Schottky contact. The output curve shows that the device operates at a sub-1 V bias. Also, the electrolyte does not affect the diode cell, and the cyclic voltammetry of the capacitor cell does not indicate a faradic process between AgNW and the top-gate electrode. From the transfer curve, we extracted an ION/IOFF ratio of 104, an on-current density of 65.3 mA/cm2 and a normalized transconductance of 113.4 S/cm2. Our contribution places the ZnO-EGVFET structure on the front line to develop printed transistors without a high-resolution pattern.

DC and RF analysis of vertical 3D p-type silicon nanotube FET for low power applications

ABSTRACT A vertical p-type 3D silicon nanotube field effect transistor (p-type Si-NTFET) is designed and simulated by using the tool Sentaurus Technology computer-aided design (TCAD). To improve the performance with reduced short channel effects, Si-NTFET device is created with inner and outer gate structures. The performance of the proposed device is analysed in terms of outer gate length. The vertical 3D p-type Si-NTFET gives an on state current (I ON) of −2.084 × 10−3 A/µm, off state current of (I OFF) of −2.457 × 10−12A/µm and subthreshold swing of the p-type Si-NTFET device is 53 mV/dec at V DS of −0.3 V. The obtained I ON/I OFF ratio of the device is 109. The capacitances (C GD, C GG) and the transconductance (g m) and cutoff frequency (f t) of the device are also analysed. The simulated p-type Si-NTFET device has proved that the device is suitable for low-power applications.

Performance enhancement of GaSb vertical nanowire p-type MOSFETs on Si by rapid thermal annealing

GaSb is considered as an attractive p-type channel material for future III-V metal-oxide-semiconductor (MOS) technologies, but the processing conditions to utilize the full device potential such as low power logic applications and RF applications still need attention. In this work, applying rapid thermal annealing (RTA) to nanoscale GaSb vertical nanowire p-type MOS field-effect transistors, we have improved the average peak transconductance (g m,peak) by 50% among 28 devices and achieved 70 μS μm−1 at V DS = −0.5 V in a device with 200 nm gate length. In addition, a low subthreshold swing down to 144 mV dec−1 as well as an off-current below 5 nA μm−1 which refers to the off-current specification in low-operation-power condition has been obtained. Based on the statistical analysis, the results show a great enhancement in both on- and off-state performance with respect to previous work mainly due to the improved electrostatics and contacts after RTA, leading to a potential in low-power logic applications. We have also examined a short channel device with L g = 80 nm in RTA, which shows an increased g m,peak up to 149 μS μm−1 at V DS = −0.5 V as well as a low on-resistance of 4.7 kΩ·μm. The potential of further enhancement in g m via RTA offers a good alternative to obtain high-performance devices for RF applications which have less stringent requirement for off-state performance. Our results indicate that post-fabrication annealing provides a great option to improve the performance of GaSb-based p-type devices with different structures for various applications.

Benefits of using arrays of vertical nanowire FETs in integrated circuits to mitigate variability

We investigate the benefits of the use of arrays of vertical nanowire (vNW) field-effect transistors (FETs) to implement integrated circuits. By means of technology computer aided design and circuit simulations, the optimal dimensions of the vNWFETs are determined. Device and circuit variability levels have been investigated. The benefits of using array configurations are the decrease of the response time and a significant mitigation of the variability level as the number of the elements in the array increases.

The beneficial impact of a p–p + junction on DC and analog/radio frequency performance of a vertical super‐thin body FET

This article investigates the impact of the p–p+ junction (at the body-substrate interface) on different direct current (DC) and analog/radio frequency (RF) performance parameters of a newly invented structure called vertical super-thin body field effect transistor (VSTB FET) through a well-calibrated TCAD tool. At a fixed body doping, the influence of p–p+ junction was inspected for different substrate doping (Ns); which reveals that Ns has a robust control on the device electrostatics. Interestingly, higher Ns is seen to significantly suppress different short channel effects (SCEs), which in turn helps to improve various DC parameters excellently. An increase in Ns from 1015 to 1018 cm−3 improves off-state leakage current and on-to-off current ratio by three orders of magnitude. Also, such a change in Ns decreases subthreshold swing and drain-induced-barrier-lowering by 8.78 mV/dec and 11.15 mV/V, respectively. The underlying physics behind such improvement at higher Ns is explored through the off-state channel electron density profiles corresponding to different Ns values. Further, different analog/RF parameters such as transconductance, input capacitance, gate-drain capacitance, output conductance, gain-bandwidth-product, and transconductance frequency product (TFP) show slight improvement for increasing Ns. In contrast, TGF, GFP, and GTFP offer large enhancement at higher Ns. This study is expected to demonstrate the significance of Ns on device performance.

Novel Vertical Power MOSFET With Step Hk Insulator Close to Super Junction Limit Relationship Between Breakdown Voltage and Specific ON-Resistance by Improving Electric Field Modulation

A new vertical double-diffused metal oxide semiconductor field effect transistor (MOSFET) is presented based on the high- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${k}$ </tex-math></inline-formula> (Hk) MOSFET concept in this article with the step high- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${k}$ </tex-math></inline-formula> insulator, named as step Hk vertical double-diffused metal oxide semiconductor (VDMOS), to improve the electric field modulation effect. For step Hk VDMOS, the depletion is increased by the electric field modulation effect of step Hk insulator, which decreases the specific on-resistance of step Hk VDMOS compared to the conventional Hk VDMOS. The various thickness of the Hk insulator modulates the vertical electric field distribution in the drift region, which increases the breakdown voltage (BV) of the step Hk VDMOS. Meanwhile, an analytical model for novel step Hk VDMOS is obtained by solving the 2-D Poisson equation in an N-type drift region, and the 2-D Laplace equation in the step Hk region, which can reasonably explain the modulation effect of the step Hk region on the electric field distribution. The results show that the BV of the step Hk VDMOS is increased from 639 V of the conventional Hk VDMOS to 736 V with the same drift length of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$42~\mu \text{m}$ </tex-math></inline-formula> . The theoretical results of the electrical characteristics are in good agreement with the results from numerical simulations.