Vertical Electric Field Distributions Research Articles

Novel Vertical Power MOSFET With Step Hk Insulator Close to Super Junction Limit Relationship Between Breakdown Voltage and Specific ON-Resistance by Improving Electric Field Modulation

A new vertical double-diffused metal oxide semiconductor field effect transistor (MOSFET) is presented based on the high- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${k}$ </tex-math></inline-formula> (Hk) MOSFET concept in this article with the step high- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${k}$ </tex-math></inline-formula> insulator, named as step Hk vertical double-diffused metal oxide semiconductor (VDMOS), to improve the electric field modulation effect. For step Hk VDMOS, the depletion is increased by the electric field modulation effect of step Hk insulator, which decreases the specific on-resistance of step Hk VDMOS compared to the conventional Hk VDMOS. The various thickness of the Hk insulator modulates the vertical electric field distribution in the drift region, which increases the breakdown voltage (BV) of the step Hk VDMOS. Meanwhile, an analytical model for novel step Hk VDMOS is obtained by solving the 2-D Poisson equation in an N-type drift region, and the 2-D Laplace equation in the step Hk region, which can reasonably explain the modulation effect of the step Hk region on the electric field distribution. The results show that the BV of the step Hk VDMOS is increased from 639 V of the conventional Hk VDMOS to 736 V with the same drift length of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$42~\mu \text{m}$ </tex-math></inline-formula> . The theoretical results of the electrical characteristics are in good agreement with the results from numerical simulations.

Physics-Based TCAD Simulation and Calibration of 600 V GaN/AlGaN/GaN Device Characteristics and Analysis of Interface Traps.

This study proposes an analysis of the physics-based TCAD (Technology Computer-Aided Design) simulation procedure for GaN/AlGaN/GaN HEMT (High Electron Mobility Transistor) device structures grown on Si (111) substrate which is calibrated against measurement data. The presence of traps and activation energies in the device structure will impact the performance of a device, the source of traps and position of traps in the device remains as a complex exercise until today. The key parameters for the precise tuning of threshold voltage (Vth) in GaN transistors are the control of the positive fixed charges −5 × 1012 cm−2, donor-like traps −3 × 1013 cm−2 at the nitride/GaN interfaces, the energy of the donor-like traps 1.42 eV below the conduction band and the acceptor traps activation energy in the AlGaN layer and buffer regions with 0.59 eV below the conduction band. Hence in this paper, the sensitivity of the trap mechanisms in GaN/AlGaN/GaN HEMT transistors, understanding the absolute vertical electric field distribution, electron density and the physical characteristics of the device has been investigated and the results are in good agreement with GaN experimental data.

Novel UHF RFID Near-Field Reader Antenna with Uniform Vertical Electric Field Distribution

This paper presents two novel UHF RFID near-field reader antennas with uniform vertical electric field distribution. The two antennas have the following common characteristics. First, the radiating parts of the two antennas are simulated and fabricated by the microstrip lines and work using the leakage wave principle of microstrip lines. Second, the end of microstrip lines match the load to form a traveling wave mode of operation, so the two antennas have broadband characteristics. Third, both antennas are fed in a coaxial manner at the center of the antenna. The simulation and measurement results can show that the proposed three-branch antenna and four-branch antenna achieve good impedance matching in the range of 883–960 MHz and 870–960 MHz, respectively, and achieve uniform distribution of the vertical electric field component in a certain area. The reading areas of the three-branch antenna and the four-branch antenna are 70 mm × 70 mm × 90 mm and 100 mm × 100 mm × 120 mm (length × width × height), respectively. Due to the introduction of the ground plate, the antenna gain is low, which meets the design requirements of near-field antennas.

Floating Ni Capping for High-Mobility p-Channel SnO Thin-Film Transistors.

We utilized Ni as a floating capping layer in p-channel SnO thin-film transistors (TFTs) to improve their electrical performances. By utilizing the Ni as a floating capping layer, the p-channel SnO TFT showed enhanced mobility as high as 10.5 cm2·V−1·s−1. The increase in mobility was more significant as the length of Ni capping layer increased and the thickness of SnO active layer decreased. The observed phenomenon was possibly attributed to the changed vertical electric field distribution and increased hole concentration in the SnO channel by the floating Ni capping layer. Our experimental results demonstrate that incorporating the floating Ni capping layer on the channel layer is an effective method for increasing the field-effect mobility in p-channel SnO TFTs.

A breakdown model of LDMOS optimizing lateral and vertical electric field to improve breakdown voltage by multi-ring technology

An analytical model for the breakdown voltage (BV) of a Lateral Double-diffused Metal Oxide Semiconductor field-effect transistor with a Multi-Ring structure (M-R LDMOS) is presented. The proposed analytical model is obtained by solving Poisson’s equation in cylindrical coordinates, which can reasonably explain the modulation effect of the M-R structure on the surface and vertical electric field distributions at the same time, and accurately describe the potential and electric field distributions of the M-R structure. As well as the lateral, vertical and radial BVs are formulized to predict the breakdown behaviors. In the paper, all the analytical results can be validated by numerical results obtained by Sentaurus Technology Computer Aided Design (TCAD) simulation, showing the accuracy of the proposed model. It is worth noting that the proposed analytical model is applicable to lateral power devices with an M-R structure.

New Super-Junction LDMOS Breaking Silicon Limit by Multi-Ring Assisted Depletion Substrate

A novel super-junction (SJ) lateral double-diffused MOSFET with the multi-ring substrate (M-R SJ-LDMOS) is proposed for the first time. The substrate-assisted depletion (SAD) effect is eliminated by the n-type M-R to realize a balanced symmetric SJ with the low specific ON-resistance ( ${R}_{\text {on,sp}}$ ). Meanwhile, more uniform lateral and vertical electric field distributions are obtained under the surface and bulk electric field modulation effect, which leads to the enhancement of breakdown voltage (BV). The simulation results show that the BV of M-R SJ-LDMOS is increased by 427.2% and 81.2% in comparison with the conventional SJ-LDMOS and buffered step doping (BSD) SJ-LDMOS with the same drift region length, respectively. In addition, ${R}_{\text {on,sp}}$ of M-R SJ-LDMOS is reduced by 18.6% and 80.3% than that of BSD SJ-LDMOS and the conventional SJ-LDMOS. The figure-of-merit (FOM) of M-R SJ-LDMOS is 5.81 MW/cm2, which means the performance of M-R SJ-LDMOS is so excellent to break the silicon limit. +Moreover, the application of highly doped substrate ( ${3} \times {10}^{{15}}$ cm−3) in M-R SJ-LDMOS cuts the cost of substrate.

Vertical double diffused MOSFET with step HK insulator improving electric field modulation

A novel step high- k metal-oxide-semiconductor field-effect transistor (step HK-MOSFET) is designed with the step high- k insulator based on the HK-MOSFET concept for the first time. In the off-state, the step HK insulator enhances the lateral field component in the drift region due to the new electric field peak, which increases the depletion of the drift region and leading to the low specific on-resistance ( R on, sp ) of step HK-MOSFET compared with the conventional HK-MOSFET. Meanwhile, the various thicknesses of the HK insulator modulates the vertical electric field distribution in the drift region, which increases the breakdown voltage (BV) of step HK-MOSFET compared with the conventional vertical double diffused MOSFET and HK-MOSFET. The results show that the simulated BV of step HK-MOSFET is increased from 639 V of the conventional HK-MOSFET to 736 V with the same drift region length of 42 μm or decreased the requirement of permittivity for the HK region to 120 e 0 from 230 e 0 with the same BV of 600 V.

Numerical Analysis of the LDMOS With Side Triangular Field Plate

A Lateral Double-diffused Metal Oxide Semiconductor (LDMOS) with side triangular field plate (STFP) is proposed for improving the breakdown voltage ( BV ) and reducing the specific on-resistance ( $R_{on,sp}$ ). The main feature of the novel LDMOS is the STFPs at both ends of the drift region, and they are fabricated into the dielectric pillars. With the introduction of the STFPs, the electric field peaks at the P-well/N-drift and N+/N-drift junctions are reduced effectively. The STFPs together with the dielectric pillars modulate the surface and vertical electric field distributions, which enhances the BV . Meanwhile, the doping concentration of the silicon pillars in the drift region is optimized and thus reduces the $R_{on,sp}$ . The simulation results indicate that the BV of 379 V and the $R_{on,sp}$ of 37.3 $\text{m}\Omega \cdot $ cm2 are achieved by the STFP-LDMOS. The figure of merits ( FOM ) of the STFP-LDMOS is 2.7 times compared with the conventional LDMOS without STFPs. The STFP-LDMOS demonstrates a great trade-off between the $R_{on,sp}$ and BV .

An Investigation of Electric Field and Breakdown Voltage Models for a Deep Trench Superjunction SiC VDMOS

The theoretical analysis of breakdown model for a deep trench superjunction (DT-SJ) SiC VDMOS is presented in this paper. The vertical electric field distribution is derived by the electric field decomposition. Then, a fitting dependence of the critical electric field on the doping concentration for the device is obtained, based on which, the model of breakdown voltage is given for the DT-SJ SiC VDMOS. Analytical results are compared with simulative results with the same thicknesses of drift region from $8~\mu \text{m}$ to $16~\mu \text{m}$ and the doping concentrations from $4\times 10^{16}$ cm $^{-3}$ to $8\times 10^{16}$ cm $^{-3}$ . It is numerically demonstrated that the errors between model and simulation are less than 3% when N pillar and P pillar have the same width of $1\mu \text{m}$ .

A Novel Pinned Cover Design With an Array of Three-Dimensional n-Pole Elements for Low-Frequency Filtering of Microwave Circuit Packages

In the proposed study, a novel miniaturized cover design including three-dimensional (3-D) n -pole (two-, three-, and four-pole) elements, instead of a conventional pinned cover consisting of an array of pins with circular cross section, is suggested to move the bandgap to lower frequencies. The frequency response of the proposed cover design is numerically compared with the conventional pinned cover to show the effect of the number of poles on the filter performance. Furthermore, an experimental study is performed for miniaturized cover with a 5 × 5 array of 3-D three-pole elements to validate the numerical results. Finally, a simple S-shaped 50-Ω microstrip transmission line is built and mounted on the cavity, and the magnitude of the scattering parameters as well as the vertical electric field distributions are compared for the cases with and without an array of 3-D three-pole elements to demonstrate the cavity mode suppression.

Novel LDMOS Optimizing Lateral and Vertical Electric Field to Improve Breakdown Voltage by Multi-Ring Technology

A novel lateral double-diffused MOSFET with multi-ring substrate (M-R LDMOS) is proposed. New high electric field peaks are introduced by the M-R due to the effect of the electric field modulation, which makes the lateral and vertical electric field distributions more uniform at the same time. As a consequence, the breakdown voltage (BV) of M-R LDMOS is enhanced significantly. The simulation result shows that the BV of M-R LDMOS is 566 V with the drift region length of $30~\mu \text{m}$ . Furthermore, the figure-of-merit of M-R LDMOS is 3.05 MW/cm2, increased by 190%, 45%, and 24.5% in comparison with the conventional LDMOS, the step doping drift LDMOS, and the assisted deplete-substrate layer LDMOS, respectively. M-R LDMOS has a much better performance. In addition, the proposed M-R LDMOS uses the highly doped substrate ( $3\times 10^{15}$ cm−3), which significantly reduces the cost of substrate.

The Effect of Drain Bias Stress on the Instability of Turned-OFF Amorphous HfInZnO Thin-Film Transistors Under Light Irradiation

A comprehensive study was done regarding stabilities under simultaneous stress of light and negative gate bias ( $V_{\mathrm{ G}}$ )/positive drain bias ( $V_{\mathrm{ D}}$ ) in amorphous hafnium-indium–zinc-oxide thin-film transistors. Negative threshold voltage ( $V_{\mathrm {\mathbf {th}}}$ ) shift was observed in transfer characteristics after the stress. Through the consecutive stresses of ( $V_{\mathrm{G}}= -5$ V, $V_{\mathrm{D}}= 15$ V, and $V_{\mathrm{ S}}= 0$ V) and ( $V_{\mathrm{G}}= -5$ V, $V_{\mathrm{D}}= 0$ V, and $V_{\mathrm{S}}= 15$ V) under light illumination, it is found that the negative $V_{\mathrm {\mathbf {th}}}$ shift is affected only by $V_{\mathbf {G}}$ , because the drain current is determined by source-side energy barrier though drain-side energy band is locally lowered by $V_{\mathrm{D}}$ -induced drain-side trapped holes. Furthermore, the drain-side trapped holes increase ON-current by reducing channel resistance after channel accumulation. Gate-to-drain capacitance ( $C_{\mathrm {\mathbf {GD}}}$ ) was measured before/after the ( $V_{\mathrm{G}}= -5$ V, $V_{\mathrm{D}}= 15$ V, and $V_{\mathrm{S}}= 0$ V) stress to clarify the presence and distribution of the drain-side trapped holes. From $C_{\mathrm {\mathbf {GD}}}$ stretching out after the stress, it is revealed that the trapped holes introduce an additional capacitance by responding to the accumulated electrons and the capacitance is distributed according to the vertical electric field distribution of the stress.

An analytical model for the vertical electric field distribution and optimization of high voltage REBULF LDMOS

In this paper, an analytical model for the vertical electric field distribution and optimization of a high voltage-reduced bulk field (REBULF) lateral double-diffused metal—oxide-semiconductor (LDMOS) transistor is presented. The dependences of the breakdown voltage on the buried n-layer depth, thickness, and doping concentration are discussed in detail. The REBULF criterion and the optimal vertical electric field distribution condition are derived on the basis of the optimization of the electric field distribution. The breakdown voltage of the REBULF LDMOS transistor is always higher than that of a single reduced surface field (RESURF) LDMOS transistor, and both analytical and numerical results show that it is better to make a thick n-layer buried deep into the p-substrate.

Dual Gate Indium–Zinc Oxide Thin-Film Transistors Based on Anodic Aluminum Oxide Gate Dielectrics

In this paper, we propose a dual gate thin-film transistor (TFT) based on anodic aluminum oxide gate dielectrics and investigate the top gate (TG) effect on device performance. It is shown that the threshold voltage of TFTs could been linearly modulated with respect to the applied TG voltage due to the modification of vertical electric field distribution between the bottom gate and top gate. In addition, the introduction of top gate would lead to the asymmetric control of threshold voltage modulation by the variation of bottom gate-dielectric and TG-dielectric, which makes it attractive in the TFT fabrication for intensive use. Moreover, the additional TG can provide an effective light shielding that guarantee the electrical reliability of TFTs under negative bias illumination stress with only − 0.37 V shift of threshold voltage after 9000 s. Owning to its linear controllability of threshold voltage, it is believed that the dual-gate structure will be tentatively introduced in the application of compensation pixel circuit.

Study on the strained SiGe p-channel metal-oxide-semiconductor field-effect transistor with polycrystalline silicon germanium gate threshold voltage

In this work, the strained SiGe p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET) with poly-Si1-xGex gate has been studied. Based on the analysis of vertical electric field and potential distribution, the equipment oxide thickness of strained SiGe PMOSFET with poly Si1-xGex gate is established. The mechanism and the influence of hot carriers induced are studied. A model of the drift of threshold voltage is established; its relationships with the duration of the applied electrical stress, the voltage of gate, the Ge content of the poly Si1-xGex gate and the strained SiGe are also obtained. Based on the above results, the simulation results have been compared with the experimental data. The drift of threshold voltage is 0.032 V under 10000 s electrical stress. A good agreement is observed, which indicates the validation of our proposed model.

Quantum simulation study of single halo dual-material gate CNTFETs

For the first time, a novel single halo dual-material gate carbon nanotube Field-Effect Transistors (CNTFETs) with doped source and drain extensions is proposed and simulated using quantum simulation. The simulations are based on two-dimensional non-equilibrium Green’s functions (NEGF) solved self-consistently with Poisson’s equations. Comparisons are made for electrical characteristics among four CNTFETs structures, which are conventional single-material-gate CNTFETs (C-CNTFETs), halo single-material-gate CNTFETs (HALO-CNTFETs), dual-material-gate CNTFETs (DMG-CNTFETs), and halo dual-material-gate CNTFETs (HALO-DMG-CNTFETs). The results show that the HALO-DMG structure decreases significantly the leakage current and increases on–off current ratio as well as cutoff frequency. It is also demonstrated that HALO-DMG structure possesses two perceivable steps in potential profile of the channel, which leads to another lateral electric field peak inside the channel, thus improve both carrier efficiency and the immunity against short-channel effects (SCE). Finally, the high-frequency characteristics of the CNTFETs have been discussed based on the channel vertical electric field distributions. The parasitic capacitance has a great influence on the cutoff frequency, and limits the RF performance of the device.

Electric Field Analysis of 220 kV Composite Material Tower Lines

Using the finite element analysis, this work analyzed the electric field distribution of 220kV transmission steel tower with double-circuit and composite material transmission tower with the same size, and compared the electric field effect of two materials transmission tower for surroundings. And this work compared the vertical and axial electric field distribution along transmission line of the two materials transmission tower. The results indicate the composite material tower can improve the environment of electric field near the transmission lines.

Analytical models for the electric field distributions and breakdown voltage of Triple RESURF SOI LDMOS

In this paper, analytical models for the electric field distributions and breakdown voltage of Triple RESURF SOI LDMOS are proposed. The new analytical expressions of the surface and vertical electric field distributions are presented based on which the general analytic expressions of the RESURF condition and the vertical breakdown voltage of Single, Double and Triple RESURF SOI LDMOS are derived. Dependence of the breakdown voltage and specific on-resistance on the P-layer’ parameters of Triple RESURF SOI LDMOS are discussed in detail. Both analytical and numerical results show that the specific on-resistance of Triple RESURF SOI LDMOS is reduced by 50% compared with Single RESURF SOI LDMOS at the same breakdown voltage. The analytical results are in good agreement with those of 2D simulations.

Breakdown vovtage analysis of new AlGaN/GaN high electron mobility transistor with the partial fixed charge in Si3N4 layer

In order to optimize the surface electric field of the traditional AlGaN/GaN high electron mobility transistor and improve the breakdown voltage and reliability, a new AlGaN/GaN high electron mobility transistor is proposed with the partial fixed positive charges in the Si3N4 passivation layer in this paper. The partial fixed positive charges of the Si3N4 passivation layer do not affect the polarization effect of the AlGaN/GaN heterojunction. The surface electric field tends to the uniform distribution due to the new electric field peak formed by the partial fixed positive charges, which modulates the surface electric field by applying the electric field modulation effect. The high electric fields near the gate and drain electrode decrease due to the new electric field peak. The breakdown voltage is improved from the 296V for the traditional structure to the 650V for the new structure proposed. The reliability of the device is improved due to the uniform surface electric field. The effect of the electric field modulation is explained by the horizontal and vertical electric field distribution between the Si3N4 and AlGaN interface, which provides a scientific basis for designing the new structure with the partial fixed positive charges in the Si3N4 layer. Because of the fixed positive charge compensation, the two-dimensional electron gas concentration increases, and the on-resistance decreases. So, the output current of the new structure increases compared with that of the traditional AlGaN/GaN High Electron Mobility Transistor.

Study of gate depletion effect in strained Si NMOSFET with polycrystalline silicon germanium gate

Based on the analysis of Poly-Si1-xGex gate work function and by solving Poisson equation, the models of vertical electric field and potential distribution in strained Si NMOSFET with Poly-Si1-xGex gate are obtained; threshold voltage model and the gate depletion thickness and it's normalization model are established in strained Si NMOSFET based on the above results, with the gate depletion effect of Poly-Si1-xGex taken into account. Then the influences of device geometrical and physical parameters of device especially the Ge fraction on Poly-Si1-xGex gate depletion thickness are investigated. Furthermore, the effect of gate depletion thickness on threshold voltage is analyzed. It shows that the poly depletion thickness decreases with the increases of Ge fraction and gate doping concentration, while it increases with the increase of substrate doping concentration. Furthermore, the threshold voltage increases with the increase of gate depletion thickness. The results can provide theoretical references to the design of strained Si devices.