Vertical Double Diffused MOSFET Research Articles

Study of the Within-Batch TID Response Variability on Silicon-Based VDMOS Devices

Silicon-based vertical double-diffused MOSFET (VDMOS) devices are important components of the power system of spacecraft. However, VDMOS is sensitive to the total ionizing dose (TID) effect and may have TID response variability. The within-batch TID response variability on silicon-based VDMOS devices is studied by the 60Co gamma-ray irradiation experiment in this paper. The variations in device parameters after irradiation is obtained, and the damage mechanism is revealed. Experimental results show that the standard deviations of threshold voltage, subthreshold swing, output capacitance, and diode forward voltage increase, while the standard deviation of maximum transconductance decreases after irradiation. The standard deviation of on-state resistance is basically unchanged before and after irradiation. By separating the trapped charges generated by TID irradiation, it is found that the deviation of the oxide trapped charges and the interface traps increase with the increase in the total dose. The reasons for the variation in device parameters after irradiation are revealed by establishing the relationship between the trapped charges and the electrical parameters before and after irradiation.

Switch-Mode MOSFETs for Class A Radio Frequency Amplification

Vertical double diffused MOSFETs (“VDMOSFETs”) developed for switching power supplies were successfully used in high voltage, high frequency linear amplifier circuits. These high voltage power switches are surprisingly useful for linear RF power amplifiers and transmitters. In most of their intended applications such as in switching power supplies or switched digital amplifiers, VDMOSFETs are pulsed by a high voltage and the pulsed output is heavily filtered. This avoids the linear region of the VDMOSFET, which normally limits the efficiency to a theoretical maximum of 25%. However, in a search of MOSFETs for high voltage linear amplification using Class A bias without heavy use of filtering, these low-cost switching MOSFETs were found to work best, if limited to radio frequencies above 1.5 MHz. Conditions, and in particular, very low impedance driving of the MOSFET gate, were discovered that gave efficiencies of 70%, rivaling that of non-linear pulse techniques such as Class C or Class D operation. The beneficial effect of linear operation combined with high efficiency at a high voltage is suggested to arise from Miller capacitance. This was only seen at radio frequencies and with the larger current, higher gate capacitance devices. Switching MOSFETs as described here should be considered alongside dedicated RF MOSFETs such as the more expensive LD (lateral diffused) MOSFET when working with RF power.

Novel High-Tolerance Termination With Resistive Field Plate for 600 V Super-Junction Vertical Double-Diffused MOSFET

In this letter, a novel high-tolerance termination is proposed for 600 V super-junction vertical double-diffused MOSFET (SJ VDMOS). By using a multi-ring resistive field plate between the active region and edge ring, the narrow charge tolerance of termination for small cell pitch SJ VDMOS is improved remarkably. The surface field plate can dynamically deplete the excess charges and introduce additional electric field peaks, effectively counteracting the degradation caused by charge imbalance. Combined with the symmetrical folded layout, the tolerance of the P-type lateral connection (LC) layer reaches ±21.7%, and the design window of the P-pillar extends to the same range as that of the active region. This provides great flexibility for the design of the LC layer and even JFET and P-pillar implantation.

Static and Transient Simulation of 4H-SiC VDMOS Using Full-Band Monte Carlo Simulation That Includes Real-Space Treatment of the Coulomb Interactions

In this article, we present a novel full-band Monte Carlo device simulator for modeling 4H-SiC power electronic devices in which, for the first time, the Coulomb interactions have been accounted for through a real-space molecular dynamics approach. Proper treatment of the electron–electron interactions is critical for modeling power electronic devices because of the high electron densities. In addition, because of the high applied voltages, the use of a full-band Monte Carlo device simulator is a must. The simulator has been successfully used to explain on a physical basis the steady-state and the switching behavior of a 3-D vertical double-diffused MOSFET (VDMOS) fabricated in the 4H-SiC technology.

Optimized JFET regions of 4H-SiC VDMOS with reduced on-resistance and improved gate oxide reliability

SiC is an attractive semiconductor for high power applications and the vertical double-diffused MOSFET (VDMOS) is a promising structure for SiC power devices. However, there is a trade-off between the on-resistance of VDMOS and its gate oxide layer reliability. In order to reconcile the contradictions induced by the intrinsic semiconductor device physics, an optimized junction field effect transistor region is designed and fabricated to dramatically decrease the on-resistance of VDMOS without sacrificing its gate oxide layer reliability and blocking characteristic. The specific on-resistance can reach 16 mΩ · cm2 by on-chip measurements with a low electric field in the gate oxide and a super-high breakdown voltage up to 1819 V. The conciliation of the on-resistance and gate oxide layer reliability of VDMOS is a promising candidate for mass production of SiC power applications.

Total Ionizing Dose Effects in 30-V Split-Gate Trench VDMOS

In this article, the total ionizing dose (TID) effect is investigated in the 30-V split-gate trench (SGT) Vertical double diffused MOSFET (VDMOS). The complex trench structure, including gate oxide, split-gate oxide, and isolation oxide, is carefully studied to reveal the degradation mechanisms. Due to the multioxidation and annealing processes, the trench structure suffers serious oxide defeats. The analytical result shows a larger trapping efficiency ( ${f}_{{\text {ot}}}$ ) compared to the planar gate technology, leading to significant ${V}_{{\text {th}}}$ shifts and subthreshold leakage. Meanwhile, irradiation-induced trapped charges in the split-gate oxide have a great influence on the electric field profile in bulk, which gives rise to breakdown voltage (BV) degradation. The experimental result shows that BV presents a gradient descent and drops to as low as 14 V at 100 krad(Si). Through TCAD simulation and analytical calculation, these TID responses are evaluated, and three approaches have been proposed for the radiation hardness of SGT VDMOS.

SiC gate‐controlled bipolar‐field‐effect composite transistor with large on‐state current

In this work, a novel bipolar-field-effect composite transistor based on silicon carbide (SiC) Vertical Double-diffused MOSFET (VDMOS) is proposed and investigated for the first time. The novel device is controlled by a gate and is a composite structure of a parasitic Bipolar Junction Transistor (BJT) and a Vertical Double-diffused MOSFET (VDMOSFET), called SiC GCBT (SiC Gate-Controlled Bipolar-field-effect composite Transistor). The structure features using the base-gate short connection mode, instead of the base-source short connection mode, as the traditional SiC VDMOS. So that two conductive channels can be provided by the parasitic bipolar transistor and the metal oxide semiconductor structure for the new device, which not only can improve the integration degreebut also greatly increases the on-state current while the breakdown mechanism remains unchanged. As simulation results show that, compared to the traditional SiC VDMOS with the same parameters, SiC GCBT has the identical BV (about 800 V) and a V th (2.98 V) that is reduced by a factor of 3, and its on-state current is 16.7 times larger than that of SiC VDMOS and is almost unaffected by the width of the Junction Field-Effect Transistor (JFET) region. In addition, under the same gate-controlled voltage, its switching speed can even be compared with that of the traditional SiC VDMOS.

Vertical double diffused MOSFET with step HK insulator improving electric field modulation

A novel step high- k metal-oxide-semiconductor field-effect transistor (step HK-MOSFET) is designed with the step high- k insulator based on the HK-MOSFET concept for the first time. In the off-state, the step HK insulator enhances the lateral field component in the drift region due to the new electric field peak, which increases the depletion of the drift region and leading to the low specific on-resistance ( R on, sp ) of step HK-MOSFET compared with the conventional HK-MOSFET. Meanwhile, the various thicknesses of the HK insulator modulates the vertical electric field distribution in the drift region, which increases the breakdown voltage (BV) of step HK-MOSFET compared with the conventional vertical double diffused MOSFET and HK-MOSFET. The results show that the simulated BV of step HK-MOSFET is increased from 639 V of the conventional HK-MOSFET to 736 V with the same drift region length of 42 μm or decreased the requirement of permittivity for the HK region to 120 e 0 from 230 e 0 with the same BV of 600 V.

The threshold voltage degradation model of N Channel VDMOSFETs under PBT stress

With the voltage increasing in DC power systems, positive bias temperature instability (PBTI) induced gate oxide degradation of commercial n-channel power vertical double diffused MOSFETs (VDMOSFETs) has been greatly enhanced recently. However, it is not mature in some aspects, e.g., parametric models of PBTI and the turn-around phenomenon are rarely studied. Aiming at these disadvantages, the experimental study and the argument are proposed in this paper. First, the simulation was used to identify and verify the threshold voltage as the characteristic parameter and the accelerated experiment test was conducted to collect data for degradation modeling. Then, a Power law-Arrhenius combined model was adopted in the degradation model to take into account the electrical and thermal influence. Besides that, a two-phase PBTI degradation model was presented, which can describe the turn-around phenomenon. Moreover, the comparison of the estimated remaining useful life (RUL) results with the experimental data verified the accuracy of the developed model.

SiC/Si heterojunction VDMOS breaking silicon limit by breakdown point transfer technology

An innovative semiconductor power vertical double-diffused MOSFET (VDMOS) is proposed for the first time with the SiC/Si heterojunction at the P-base and N-drift region (called for SiC/Si VDMOS), which improves the trade-off between the breakdown voltage ( BV ) and specific on-resistance ( R on,sp ). The `soft' Si material has been combined with the `hard' SiC material to play their own advantages for SiC/Si VDMOS. The Si has been formed above the 6H-SiC substrate to make up the channel and source electrode, and the 6H-SiC is underneath the P-base to form the SiC/Si heterojunction. The novel terminal technology of breakdown point transfer has been advanced for the first time and applied to SiC/Si VDMOS, which transfers the breakdown point of SiC/Si VDMOS and improve the BV compared with Si VDMOS. The simulated results have been shown that the optimised BV of proposed SiC/Si VDMOS is increased from 226 to 578 V compared with the conventional Si VDMOS with the same drift region length, which is because the breakdown point is transferred from the higher electric field area with the maximum curvature radius to the low electric field area. The simulated R on,sp of SiC/Si VDMOS is 17.4 mΩ·cm 2 with the BV of 578 V, which is lower than that of 41.01 mΩ·cm 2 with the BV of 226V in Si VDMOS. The silicon limit relationship has been broken for SiC/Si VDMOS.

Analysis on the Rapid Recovery of Irradiated VDMOSFETs by the Positive High Electric Field Stress

High electric field stress (HEFS) and annealing effects on irradiated (by 60Co $\gamma$ -ray) vertical double-diffused MOSFETs (VDMOSFETs) are investigated. The behaviors of the oxide-trapped charges and interface traps during the stress are measured by using a simplified midgap technique. Rapid recovery of the threshold voltage ( $V_{\mathrm {th}}$ ) for the irradiated VDMOSFET is observed under a positive high electric field stress (PHEFS). The results show that the densities of oxide-trapped charges and interface traps decreased more rapidly for the PHEFS than that for postirradiation annealing. Repeated irradiation results of PHEFS-recovered VDMOSFETs indicate the possibility of reusing the irradiated VDMOSFETs.

Measurement and modeling of gate–drain capacitance of silicon carbide vertical double-diffused MOSFET

Silicon carbide (SiC) is considered as one of the key materials to realizing device operations in high-temperature, high-frequency, and high-power applications. When designing circuits in such applications, an accurate simulation model for SiC power MOSFETs is important. Among others, the gate–drain capacitance, Cgd, is particularly important in building the SiC MOSFET model because the capacitance significantly affects switching behavior of the device. In this paper, a Cgd model, which is based on a unified representation of surface potential, is proposed for enhancing the accuracy of circuit simulations. By considering the operation of vertical power SiC MOSFETs, the proposed capacitance model correctly accounts for the capacitance modulation effect due to the channel that is formed when the gate voltage is higher than the drain voltage. In addition, a Cgd measurement method is also proposed in order to characterize Cgd in a wider voltage range. Through experiments using a commercial SiC power MOSFET, it is demonstrated that the proposed model successfully approximates the capacitance in a wide range of bias voltages without stitching separate equations. It is also demonstrated that the proposed model is twice as accurate as the conventional one.

Modelling of Degraded Power MOSFET Effects on Inverter Static Parameters

In this study, electrical constant stress method which is one of accelerated tests is applied to power vertical double diffused MOSFETs continued up to 6hours. The stress induced changes of characteristic parameters (threshold voltage, mobility, etc.) of power MOSFETs are extracted. A resistive load NMOS inverter is set up and degraded power MOSFET effects on its static parameters are investigated experimentally. Besides the obtained experimental results, a simple circuit model is proposed to simulate the stress induced changes in NMOS inverter static parameters. In this manner, obtained experimental results are supported by simulation study. Proposed degradation model has ability to help designers to predict circuit reliability in the early stages of design.

Negative bias temperature instability in p-channel power VDMOSFETs: recoverable versus permanent degradation

In this study, which is aimed at assessing a possible relationship between the recoverable and permanent components of negative bias temperature instability (NBTI) degradation, we investigate NBTI in commercial IRF9520 p-channel VDMOSFETs (vertical double diffused MOSFETs) stressed under particular pulsed bias conditions by varying the pulse on-time while keeping the off-time constant and vice versa. The stress-induced threshold voltage shifts are found to be practically independent of duty cycle when the pulse on-time is kept short or the off-time is kept long, and are found to start increasing with duty cycle only when the on-time is increased or the off-time is decreased beyond specific values. These results, which are discussed in terms of dynamic recovery effects and the mechanisms leading to NBTI degradation, point to the existence of an important correlation between the recoverable and permanent components of degradation.

Research of Single-Event Burnout in Power Planar VDMOSFETs by Localized Carrier Lifetime Control

This paper presents 2-D numerical simulation results of single-event burnout (SEB) in power planar vertical double-diffused MOSFET (VDMOSFET) with localized carrier lifetime control. A low carrier lifetime control region (LCLCR) is introduced to accelerate the recombination rate of the generated holes caused by an ion's impact. The optimal localized range with LCLCR in epitaxial layer has been investigated. The SEB inhibition mechanism with LCLCR is analyzed and discussed. A VDMOSFET with localized LCLCR can operate like a normal VDMOSFET and can have improved SEB performance effectively. In addition, the leakage current density in breakdown characteristics of VDMOSFET is studied based on the variation of carrier lifetime.

Off-state drain breakdown mechanisms of VDMOS with anti-JFET implantation

Efficiency, reliability, and cost are the important design considerations of a vertical double diffused MOSFET (VDMOS) because of its high-voltage applications in consumer electronics. To minimize the cost, the devices were normally fabricated on an epitaxial layer which was grown on a highly-doped substrate. Meanwhile, it was proposed that the efficiency of a VDMOS can be enhanced by conducting an anti-JFET implant to reduce the “ON” resistance of the transistor. This paper reports the effects of anti-JFET implant on the reliability and the blocking capability of the VDMOS. Experimental results show that the anti-JFET implant can reduce the ON resistance by suppressing the channel depletion due to the parasitic JFET and enhance the breakdown voltage by moving the high-field region to the surface channel region. However, it deteriorates the device reliability greatly because the oxide quality was deteriorated and the hot holes generated in the surface high-field region could be easily injected into the gate oxide and hence caused larger subthreshold conduction and drain breakdown at lower voltage.

A Low-Voltage Planar Power MOSFET With a Segmented JFET Region

A new low-voltage planar power MOSFET with a segmented junction field effect transistor (JFET) region is proposed and demonstrated in this paper. The segmented JFET region consists of alternating n- and p-regions formed by using ion implantation, and it is fully depleted before the drain-source breakdown voltage is reached to provide a high breakdown voltage. The new planar power MOSFET allows a smaller gate-drain overlap area, a shallower p-body, and a JFET region with a doping concentration higher than those of the conventional vertical double-diffused MOSFETs (VDMOSFETs). The new structure with a breakdown voltage of 34 V is fabricated by using a 0.5-mum technology and is compared with the conventional VDMOSFET. The gate-drain charge density and the figure-of-merit are improved by 51% and 48%, respectively. However, the specific on-resistance of the device is increased by 5% due to the smaller conducting area in the segmented JFET region. Simulation results show that the figure-of-merit of the new structure is very favorable compared to those of commercial devices at the same voltage rating.

High performance power VDMOSFETs with a split-gate floating np-well design

Low gate charge power vertical double-diffused MOSFET devices are required for high-frequency systems. In this study, we proposed a split-gate with a floating np-well structure, which realizes a low gate charge performance without significantly degrading the breakdown voltage. The proposed structure removes the partial gate area between the gate and drain overlap area, and combines with an additional np-well. By this approach, the gate charge and switching loss can be reduced, and the breakdown voltage can be sustained. The gate–drain charge and gate charge of the split-gate with an np-well structure are 41.4% and 66.1% of the conventional device, respectively. These improvements are beneficial for reducing the switching loss of the devices.

Design of a rugged 60 V VDMOS transistor

Vertical double diffused MOSFET (VDMOS) is an established technology for high-current power-switching applications such as automotive circuits. The most serious failure mode is destructive damage during inductive switching, resulting from avalanche breakdown of the forward-blocking junction in the presence of high current flow. Improving the ruggedness of the device is achieved by enhancing its ability to absorb inductive energy under avalanche conditions. The purpose of the paper is to explore the possibility of improving the ruggedness of VDMOS through TCAD simulations. A p+-strip buried underneath an n+-source is proposed to suppress the turn-on of the parasitic bipolar transistor. VDMOS transistors with this design modification are expected to have higher ruggedness while maintaining its superior figure-of-merit.

Electrothermal characterization of silicon-on-glass VDMOSFETs

Electrothermal consequences of implementing bulk-silicon RF power MOS processes in the silicon-on-glass substrate transfer technology are investigated in this paper. Fabricated silicon-on-glass vertical double-diffused MOSFETs are measured on-wafer and very large thermal resistance values are extracted for each design. The influence of the thermal resistance on RF performance is analyzed, and it is shown that strong electrothermal feedback severely lowers the power capability and strongly increases the operating temperature. A combination of low-thermal contacting and surface mounting to thermally conducting printed circuit board is shown to be very efficient in reducing the large thermal resistance. Numerical thermal simulations demonstrate that surface-mounted silicon-on-glass transistors can have lower thermal resistance than the bulk-silicon device with a wafer thickness reduced down to 100 μm.