Abstract
SiC is an attractive semiconductor for high power applications and the vertical double-diffused MOSFET (VDMOS) is a promising structure for SiC power devices. However, there is a trade-off between the on-resistance of VDMOS and its gate oxide layer reliability. In order to reconcile the contradictions induced by the intrinsic semiconductor device physics, an optimized junction field effect transistor region is designed and fabricated to dramatically decrease the on-resistance of VDMOS without sacrificing its gate oxide layer reliability and blocking characteristic. The specific on-resistance can reach 16 mΩ · cm2 by on-chip measurements with a low electric field in the gate oxide and a super-high breakdown voltage up to 1819 V. The conciliation of the on-resistance and gate oxide layer reliability of VDMOS is a promising candidate for mass production of SiC power applications.
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