A Low-Voltage Planar Power MOSFET With a Segmented JFET Region

Abstract

A new low-voltage planar power MOSFET with a segmented junction field effect transistor (JFET) region is proposed and demonstrated in this paper. The segmented JFET region consists of alternating n- and p-regions formed by using ion implantation, and it is fully depleted before the drain-source breakdown voltage is reached to provide a high breakdown voltage. The new planar power MOSFET allows a smaller gate-drain overlap area, a shallower p-body, and a JFET region with a doping concentration higher than those of the conventional vertical double-diffused MOSFETs (VDMOSFETs). The new structure with a breakdown voltage of 34 V is fabricated by using a 0.5-mum technology and is compared with the conventional VDMOSFET. The gate-drain charge density and the figure-of-merit are improved by 51% and 48%, respectively. However, the specific on-resistance of the device is increased by 5% due to the smaller conducting area in the segmented JFET region. Simulation results show that the figure-of-merit of the new structure is very favorable compared to those of commercial devices at the same voltage rating.