Vertical DMOS Transistor Research Articles

Development of a Physical-Topological Model for the Response of a High-Power Vertical DMOS Transistor to the Effect of Pulsed Gamma-Radiation

A method for developing models of semiconductor devices with two-dimensional nonuniform concentration profiles of donors and acceptors in working regions of a semiconductor device structure is for the first time proposed based on a complex of physical-topological modeling of charge carrier transport and process simulation of the forming processes of the device structure. The application of process simulation is due to the need to correctly define the parameters of the semiconductor device structure, which are used as initial data to calculate the electron transport according to the physical-topological model. The parameters of production processes of ion implantation, diffusion, and lithography, which were refined during process simulation, are determined for a high-power metal—oxide—semiconductor (MOS) transistor forming by the double diffusion method in accordance with known electrical characteristics and measured geometrical sizes of the structure. This results in two-dimensional distribution profiles of donors and acceptors in p–n junctions necessary to calculate the transistor breakdown under the effect of pulsed γ radiation. Breakdown processes are modeled with the help of the physical-topological model based on the Poisson and continuity equations as well as expressions for the diffusion and drift current densities in the transistor. Accounting for carriers formed at the instant of γ irradiation is implemented by the introduction of the dependence of the generation coefficient of electron–hole pairs on the radiation-dose power. The results of calculations correlate well with the experimental data, which makes it possible to give a conclusion regarding the adequacy of the proposed complex model.

Theoretical analysis of the vertical LOCOS DMOS transistor with process-induced stress enhancement

This work presents a theoretical analysis, validated by numerical simulations, of the vertical LOCOS DMOS structure. New analytical models of the specific on-state resistance and breakdown voltage are developed, which improve upon previous models in that an explicit dependence on device geometry and impurity concentration is worked out. The model accounts for the space charge due to the lateral and vertical depletion regions related to the field plates and the p-body/ n-drift junction, respectively. The process-induced strain within the drift region is modeled as a function of the main geometrical parameters. Vertical LOCOS DMOS devices can thus be easily optimized, as shown by a few examples.

Ruggedness of Integrated VDMOS Transistors Under TLP Stress

The ruggedness of integrated vertical DMOS transistors under transmission line pulsing stress is experimentally investigated at current levels close to the thermal failure current. In addition to the parasitic vertical bipolar closest to the n-sinker contact, the lateral n-p-n transistor with the p-type junction termination as a base also goes into avalanche and supports the total current. As such, the total heat generation in the transistor is shared over a larger cross section, reducing the peak temperature. Along the device width, multiple traveling current filaments are observed; the speed of each individual filament is decreasing with the stress current. A model to predict the normalized thermal failure current I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">tf</sub> as a function of the device width is proposed. It is shown that I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">tf</sub> follows a ~W <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-0.5</sup> dependence

Measurement and modeling of the electron impact-ionization coefficient in silicon up to very high temperatures

In this paper, an experimental investigation on high-temperature electron impact-ionization in silicon is carried out with the aim of improving the qualitative and quantitative understanding of carrier transport under electrostatic discharge (ESD) conditions. Special test devices were designed and manufactured using Infineon's SPT5 technology, namely: a bipolar junction transistor (BJT), a static-induction transistor (SIT) and a vertical DMOS transistor (VDMOS), all of them with a cylindrical geometry. The measurements were carried out using a customized measurement setup that allows very high operating temperatures to be reached. A novel extraction methodology allowing for the determination of the impact-ionization coefficient against electric field and lattice temperature has been used. The experiments, carried out up to 773 K, confirm a previous theoretical investigation on impact-ionization, and widely extend the validity range of the compact model here proposed for implementation in device simulation tools. This is especially useful to predict the failure threshold of ESD-protection and power devices.

Automated setup for thermal imaging and electrical degradation study of power DMOS devices

An automated setup for investigation of degradation mechanisms in semiconductor devices under electrostatic discharge (ESD) stress is presented. Vertical-DMOS transistors of a Smart Power technology operating in bipolar snapback mode are studied by combined techniques. The current filamentary behavior imaged by a two-instants transient interferometric mapping (TIM) method and the variation of device DC characteristics are studied as a function of stress current. During repeated stress, a progressive degradation of the DC leakage current at the failure level and a slight gradual change of transfer characteristics are observed. The failure location, resolved in three dimensions by backside infrared microscopy, agrees with the position obtained from the TIM analysis and expected from device physics.

On the electrical SOA of integrated vertical DMOS transistors

The dependency of the electrical safe operating area (SOA) of an integrated vertical DMOS transistor on the layout as well as on the residual epitaxial thickness of the drift region, is experimentally investigated using transmission line pulsing experiments. Guidelines for optimizing the SOA without compromising the other device parameters are given.

Moving Current Filaments in Integrated DMOS Transistors Under Short-Duration Current Stress

Integrated vertical DMOS transistors of a 90-V smart power technology are studied under short-duration current pulses. Movement of current filaments and multiple hot spots observed by transient interferometric mapping under nondestructive snap-back conditions are reported. Device simulations show that the base push-out region associated with the filament can move from cell to cell along the drain buried layer due to the decrease of the avalanche generation rates by increasing temperature. The influence of the termination layout of the source field on the hot-spot dynamics is studied. Conditions for filament motion are discussed. The described mechanisms help homogenizing the time averaged current-density distribution and enhance the device robustness against electrostatic discharges.

Moving Current Filaments in Integrated DMOS Transistors Under Short-Duration Current Stress

Integrated vertical DMOS transistors of a 90-V smart power technology are studied under short-duration current pulses. Movement of current filaments and multiple hot spots observed by transient interferometric mapping under nondestructive snap-back conditions are reported. Device simulations show that the base push-out region associated with the filament can move from cell to cell along the drain buried layer due to the decrease of the avalanche generation rates by increasing temperature. The influence of the termination layout of the source field on the hot-spot dynamics is studied. Conditions for filament motion are discussed. The described mechanisms help homogenizing the time averaged current-density distribution and enhance the device robustness against electrostatic discharges.

High-power SOI vertical DMOS transistors with lateral drain contacts: Process developments, characterization, and modeling

Silicon-on-insulator (SOI) high-power vertical double-diffused MOS (VDMOS) transistors are demonstrated with a CMOS compatible fabrication process. A new backend trench formation process ensures a defect free device layer. Scanning electron microscope micrographs show that it is nearly free of defects. This has been achieved by moving the trench formation steps toward the end of the process. Our electrical measurements indicate that the transistors are fully functional. Electrothermal simulations show that unclamped inductive switching (UIS) test involves a substantial risk of turning the parasitic bipolar transistor (BJT) on. The UIS test is used to characterize the performance of power devices under unclamped inductive loading conditions. Extreme operating condition can be expected when all the energy stored in the inductor is released directly into device. Our measurements of the fabricated SOI VDMOSFET in the static region are in good agreement with the expected impact of the self-heating on the saturation behavior. The experiments at ambient temperature of 100/spl deg/C show that the break down voltage decreases as the drain voltage increases. This indicates that a parasitic BJT has been turned on.

Electrothermal simulations of high-power SOI vertical DMOS transistors with lateral drain contacts under unclamped inductive switching test

Electrothermal effects during the unclamped inductive switching (UIS) of silicon-on-insulator (SOI) high power vertical double diffused MOS (VDMOS) transistors have been studied by device simulation. In the UIS test all the energy stored in the inductor during the on state is dumped directly into the device when the device is turned off. This extreme condition during the UIS test will give ratings for the power device and gives a measure for the stability of the device in the breakdown regime. Electrothermal simulations of this device are evaluated under boundary conditions imposed by the UIS circuit. Simulations show that UIS involves a substantial risk of turning the parasitic bipolar transistor (BJT) on. Our measurements of the fabricated SOI VDMOSFET in the static region are in good agreement with the expected impact of the self-heating on the saturation behaviour. The experiments at ambient temperature of 100 °C show that the breakdown voltage decreases as the drain voltage increases. This indicates that the parasitic BJT has been turned on and causes an open-base bipolar transistor breakdown voltage.

Unclamped inductive switching behaviour of high power SOI vertical DMOS transistors with lateral drain contacts

The switching dynamics of silicon-on-insulator (SOI) high power vertical double diffused MOS (VDMOS) transistors with an inductive load has been investigated by device simulation. Unlike other conventional VDMOS devices, this device has drain contacts at the top surface. In general the switching behaviour of a power device during the unclamped inductive switching (UIS) test will determine the reliability of the power device as the energy stored in the inductor during the on state is dumped directly into the device when it is turned off. In this paper we compare the switching dynamics of the SOI VDMOS transistor with standard bulk silicon VDMOS device by doing numerical simulations. It is shown here, using 2D-device simulations that the power dissipated in the SOI VDMOS device during the UIS test is smaller by approximately a factor of 2 than in the standard bulk silicon VDMOSFET. The lower dissipation is due to the presence of the silicon film/buried oxide/substrate structure (this structure forms a SOI capacitor). In the case of the SOI VDMOS transistor the energy released from the inductor during the UIS test is stored to some extent in the SOI capacitor and partly dumped directly into the device. As a result the maximum current through the SOI device is separated in time from the maximum voltage across the device, unlike in the bulk case, thereby reducing the maximum power.

Self Heating Effects of High Power SOI Vertical DMOS Transistor with Lateral Drain Contacts

Self heating effects in silicon-on-insulator (SOI) high power Vertical Diffused MOS (VDMOS) transistors have been investigated by electro-thermal simulations. Unlike other conventional VDMOS devices, here we work on a modified VDMOS transistor with drain contacts at the surface. In this work we study two different aspects of this transistor namely: (1) Effect of self heating on the device performance and (2) effect of the elevated temperature on the device characteristics. Our simulation results indicate that the temperature distribution is concentrated at the drift region under the gate area and spreads down toward the drain area. The self heating effect gives a notable effect on our newly proposed VDMOS in the on-state (when Vg > Vt), and the breakdown point decreases. As we increase the ambient temperature the breakdown point decreases further.

Silicon-on-insulator approach for power IC's integrating vertical DMOS and polycrystalline silicon CMOS thin-film transistors

A novel approach for the monolithic integration of low-voltage logic and analog control circuits with vertical-current flow power transistors is described. This is achieved by fabricating a CMOS device family, using polycrystalline-silicon thin-film transistors (TFTs), on the field oxide of a single-crystal power device. Parasitic interactions between the control and power devices are eliminated in a simple, inexpensive, and easily manufacturable process. The technology is capable of supporting both MOS and bipolar power devices and the presence of the TFT circuits places no restriction on the maximum voltage or current of the power device. The TFTs exhibit good electrical characteristics and the power devices are not compromised by the addition of the TFT control circuits. This concept is demonstrated by the fabrication of a vertical DMOS power transistor with >100-V, >45-A capability, monolithically integrated with current-limiting and temperature-limiting functions. >

Model for DMOST threshold voltage

An analytical model for the channel region in MOS-gated power transistors has been developed. The model takes into account the effect of substrate doping gradient on the threshold voltage of the transistor and it can be applied to lateral and vertical DMOS and IGBT transistor structures. The model has been tested by comparing the calculated I–V characteristics for an MOS structure having various doping gradients to the results from a 2-D device simulator.

Analytical and Numerical Analysis of the Vertical DMOS Transistor Oriented to Device Modeling

Analytical and Numerical Analysis of the Vertical DMOS Transistor Oriented to Device Modeling