Vertical Constraint Graph Research Articles

Node duplication and routing algorithms for quantum-dot cellular automata circuits

Quantum-dot cellular automata (QCA) is a novel computing mechanism that can represent binary information based on the spatial distribution of electron charge configuration in chemical molecules. QCA circuit layout is currently restricted to a single layer with very limited number of wire crossings permitted. Thus, wire crossing minimisation is crucial in improving the manufacturability of QCA circuits. We present the first QCA node duplication and routing algorithms for wire crossing minimisation. Our duplication algorithm named fan-out tolerance duplication (FTD) explores node duplication in conjunction with node placement using K-layered bipartite graphs (KLBG). FTD successfully removes additional crossings at the cost of increased area and allows flexible tradeoff between area and wire crossing. Our routing algorithm, namely cycle breaker (CB), constructs a modified vertical constraint graph (VCG) to enforce additional vertical relation for wire crossing reduction. We formulate and provide a heuristic solution for the weighted minimum feedback edge set problem to effectively remove cycles from the VCG. As a result, FTD and CB achieve wire crossing results that are very close to theoretical lower bound and outperform the conventional algorithms significantly.

Arbitrary convex and concave rectilinear block packing using sequence-pair

The sequence-pair was proposed in 1995 as a representation of the packing of rectangles of general structure. Since then, there have been efforts to expand its applicability over simple rectangles. This paper proposes a unified way to represent the packing of a set of rectilinear blocks, including arbitrary concave rectilinear blocks. Our idea is in the representation of a general block by a collection of rectangle blocks with additional constraints, Some sequence-pairs of rectangle blocks with such constraints may not be feasible, i.e., there is no corresponding parking. A necessary and sufficient condition of feasible sequence-pair is given by the properties of the horizontal and vertical constraint graphs. Furthermore, it is proved that any packing is represented by a feasible sequence-pair. The condition includes dimensions of blocks involved. If we limit the rectilinear blocks to L-shaped ones, a necessary and sufficient condition can be represented only in terms of the topology of the sequence-pair, without dimensions of blocks. A packing algorithm is designed as an SA search of the generated sequence-pairs. Experimental results show the effectiveness of the proposed method.

An algorithm for finding a non-trivial lower bound for channel routing

Channel routing is a key problem in the physical design of VLSI chips. It is known that max(d max , v max ) is a lower bound on the number of tracks required in the reserved two-layer Manhattan routing model, where d max is the channel density and v max is the length of the longest path in the vertical constraint graph. In this paper we propose a deterministic polynomial time algorithm that computes a better and non-trivial lower bound on the number of tracks required for routing a channel without doglegging. This algorithm is also applicable for computing a lower bound on the number of tracks in the three-layer no-dogleg HVH routing as well as two- and three-layer restricted dogleg routing models.

EXPIDER: A channel routing expert for VLSI design

Channel routing plays an important role in VLSI (Very Large Scale Integration) design. Because of the ill-structured nature of the problem, algorithmic approaches fail to provide satisfactory solutions. Techniques using expert knowledge have been solicited and developed successfully. In this paper, we present an expert system, EXPIDER, for channel routing. Wires are placed on the tracks from the boundaries toward the middle of a channel on a track-by-track basis, with the help of weighted vertical constraint graphs. Heuristics are applied to escape from blocked states and to do directed routing without search. Tuning knowledge is provided to reduce the wire length and the number of vias. The routing area can be determined automatically without human intervention. The system was implemented in CLIPS (C Language Integrated Production System) and has been tested successfully on many cases. Some results, together with a comparison with other methods, are shown at the end of the paper.

Efficient height reduction over-the-cell channel router

The authors present a new algorithm for both two-layer and three-layer over-the-cell channel routing in the standard cell VLSI design. The approach exploits vacant terminals on the channel boundary effectively. It considers the following factors simultaneously to select net segments for routing over the cells: density distribution in the channel, the longest path in the vertical constraint graph, elimination of cycles in the vertical constraint graph and reduction in maximum cliques in the horizontal constraint graph. With respect to the PRIMARY 1 benchmark examples, the router achieved a 41.3% improvement over the Greedy channel router (one without using over-the-cell area) for a two-layer routing model and a 61.0% improvement for a three-layer routing model. This outperforms all previous algorithms.

Utilization of vacant terminals for improved over-the-cell channel routing

The WISER algorithm for over-the-cell channel routing in the standard cell design style using the two-layer routing model is presented. The novelty of this approach lies in the use of vacant terminals for over-the-cell routing. Longest paths in the vertical constraint graph and channel density are considered as a basis for choosing nets to route over the rows of standard cells. WISER has been implemented and tested on several benchmarks, including PRIMARY1 and Deutsch's difficult example. The experimental results show that WISER reduces the channel height by an average of 29%, as compared to conventional channel routers, and 15%, as compared to existing over-the-cell routers. In addition, it reduces the total number of vias per routing by 32%.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Constraint-based channel routing for analog and mixed analog/digital circuits

A well-defined methodology for mapping the constraints on a set of critical coupling capacitances into constraints in the vertical-constraint (VC) graph of a channel is presented. The approach involves directing undirected edges, adding directed edges, and increasing the weights of edges in the VC graph in order to meet crossover constraints between orthogonal segments and adjacency constraints between parallel segments while attempting to cause minimum increase in the channel height due to the constraints. Use is made of shield nets when necessary. A formal description of the conditions under which the crossover and the adjacency constraints are satisfied is provided and used to construct the appropriate mapping algorithms. The problem of imposing matching constraints on the routing parasitics in a channel with lateral symmetry is addressed. It is observed that perfect matching is not possible for a matched pair of nets with intersecting horizontal spans. A technique to achieve almost perfect mirror symmetry is presented for such pairs of nets. >

A topological sorting algorithm for three‐layer channel routing

Abstract Three‐layer channel routing is an important problem in VLSI layout. In this paper, we present a topological sorting algorithm to determine the topological order on nets depending on the operations of the vertical constraint graph (VCG) and the horizontal constraint graph (HCG). According to the order, the base router can finish the connections of all nets. In the algorithm, the HVH mode is assumed, and some examples including Deutsch's difficult example are used as test problems.

A simulated annealing channel routing algorithm

In this paper an algorithm for the Channel Routing Problem (CRP) on the Manhattan Model is proposed. The algorithm employs a search method in the solution space, known as Simulated Annealing. The channel width is reduced by breaking up thelong runs of the vertical constraint graph, associated with the problem. The dogleg strategy adopted is similar to that employed in the channel routing algorithm proposed in [1]. The results obtained by extensive simulation runs are encouraging compared with the results of other heuristics for the same problem.

Two NP-hard interchangeable terminal problems

Two subproblems that arise when routing channels with interchangeable terminals are shown to be NP-hard. These problems are: (1) determining whether there is a net-to-terminal assignment that results in an acyclic vertical and constraint graph and (2) for instances with acyclic vertical constraint graphs, obtaining net-to-terminal assignments for which the length of the longest path in the vertical constraint graph is minimum.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A Mixed HVH-VHV Algorithm for Three-Layer Channel Routing

We present a hybrid three-layer channel-routing algorithm that combines horizontal-vertical-horizontal (HVH) and vertical-horizontal-vertical (VHV) approaches [1]. The result is the best of both approaches. VHV excels when the vertical constraint graph (VCG) has long chains; HVH is strong when the VCG has a large number of incomparable nodes. In hybrid routing, the VCG is partitioned into two portions, one ideally suited for HVH and the other for VHV. The portions are routed with a transition track in between. It is shown that, for many channel-routing problems, the hybrid method can do with fewer tracks than the theoretical lower bounds of the algorithms given in [1][2][3]. A heuristic algorithm is given for determining an optimum partitioning into HVH and VHV portions. The algorithm is powerful and its performance on Deutsch's difficult example [8] is discussed as an illustration.

A Method of Improving the Terminal Assignment in the Channel Routing for Gate Arrays

The channel router, which routes a rectangular channel with two rows of terminals along its top and bottom sides, is extensively used for the automatic routing of gate arrays. It is well known that in this routing method the routing can not be performed when the vertical constraint graph contains cycles. This paper deals with the problem of eliminating cycles in the vertical constraint graph by interchanging the nets assigned to logically equivalent terminals before channel routing. A heuristic algorithm is proposed for this problem. This algorithm yields a locally optimum assignment of nets to terminals, in the sense that the number of independent cycles in the vertical constraint graph of a resultant assignment can not be reduced by interchanging any pair of the nets assigned to logically equivalent terminals. Furthermore, in order to speed up the operation of this algorithm, it is shown that the checking as to whether or not the number of independent cycles in the vertical constraint graph is reduced can be done by noting only its subgraph, when a pair of nets assigned to logically equivalent terminals are interchanged. Experimental results have indicated that this proposed algorithm is efficient.

General channel-routing algorithm

A new approach to the 2-layer channel-routing problem is introduced. The method allows horizontal and vertical connections on both layers. An order graph similar to the traditional vertical constraint graph is used in the algorithm. The main advantage is that the method is general and is immune to cyclic constraints. Furthermore, the channel width does not have a lower bound equal to the maximum density.