Vertical Bipolar Transistor Research Articles

Vertical Bipolar Transistors and a Merged 3–D Vertical Bipolar—Mos Device in Recrystallized Polysilicon

ABSTRACTThe minority carrier properties of shaped—beam laser-recrystallized polysilicon films have been studied, leading to the successful fabrication of vertical bipolar transistors in these films and to the demonstration of a novel three—dimensional mergedvertical bipolar—MOS device. Experiments with lateral transistors established a minority carrier diffusion length of 4 μm in p—type recrystallized films. Vertical bipolar npn transistors with a base—width of 0.2 μm were fabricated in 0.75–μm—thick films using a polysilicon emitter technology. The strong dependence of the gain of the transistors on hydrogen annealing steps is described. With an Ar:H plasma anneal to decrease base—emitter space—charge region recombination, a common—emitter current gain of 100 was possible. The bipolar transistor technology was then used to develop a 3—D fourterminal merged verticalbipolar—MOS device in a recrystallized film. It consists of the three terminals of a bipolar transistor plus a fourth underlying terminal which serves to switch the collector current on or off. A simple model for the device is presented.

Merged CMOS/bipolar technologies utilizing zone-melting-recrystallized SOI films

Two merged CMOS/bipolar technologies utilizing SOI structures have been demonstrated. In each case a single sequence of processing steps was used to fabricate fully isolated CMOS devices and vertical bipolar transistors on the same Si wafer. The CMOS devices were fabricated in zone-melting-recrystallized SOI film, while the bipolar devices were fabricated either in the SOI film or in epitaxial Si layers grown selectively on the Si substrate. Good electrical characteristics were obtained for the CMOS devices and for both SOI and epitaxial bipolar devices.

Vertical bipolar transistors on buried silicon nitride layers

The letter reports on the integration of vertically operating n-p-n-bipolar transistors with base widths of about 1 µm in silicon-on-insulator (SOI) structures. Nitrogen ion implantation at substrate temperatures of 550°C and subsequent SiCl 4 epitaxy provide SOI films with excellent crystalline quality. Conventional bipolar diffusion processes have been applied in order to fabricate diodes and vertical bipolar transistor arrays on thus isolated epitaxial layers. The leakage current of SOI diodes exceeds the value for bulk devices only by a factor of 2. The transistors exhibit emitter current gains of up to 100 and emitter-collector breakdown voltages of up to 35 V.

Megavolt Bioron and Arsenic Implantation into Silicon

ABSTRACTFormation of buried p-type and n-type layers in (100) silicon has been accomplished by implanting with 4 MeV boron and 11 MeV arsenic ions respectively. The projected range (Rp) of 4 MeV boron is 5.2 microns with a straggle (ΔRp) of .2 microns. The 11 MeV arsenic implant has a Rp of 4.37 microns with a ΔRp of .37 microns. The 4 MeV boron implant was carried out to a dose of l×1015/ cm2 while the 11 MeV arsenic implant dose was 1.9×1015/ cm2. For both dopants the target holder could be cooled with either liquid nitrogen (LN) or flowing room temperature water (RT). Buried amorphous regions are seen by cross sectional transmission electron microscopy (XTEM) for both boron and arsenic when LN cooling is used. Arsenic shows a buried amorphous region for the RT case as well. The extent of the buried amorphous regions are compared with the energy deposited into nuclear stopping as determined by computer simulation. Threshold levels are determined for the creation of these buried amorphous regions. The boron samples were annealed for 30 minutes at 900°C in a nitrogen ambient, and XTEM shows no residual damage for both cooling conditions. The arsenic samples underwent a two step annealing procedure; 545°C for 16 hours followed by a 945°C step for 15 minutes. Regions containing dislocation networks are observed by XTEM for both cooling conditions.The 4 MeV implanted boron buried layer was applied to an NMOS process. Transistors fabricated above the p-type buried layer show channel mobility, threshold voltage, and sub-threshold leakage which are indistinguishable from transistors fabricated without the buried layer. Vertical npn bipolar transistors have been fabricated using the 11 MeV arsenic buried layer to form the collector. Electrical characteristics from both these devices indicate that megavolt ion implantation can be applied to silicon for active device geometries.