Verilog-A Model Research Articles

Device and circuit-level performance evaluation of DG-GNR-DMG vertical tunnel FET

This work presents the comparative study of Graphene Nanoribbon (GNR) based channel Double Gate (DG) Dual Gate Material (DMG) Vertical tunnel Field Effect Transistor (VTFET) performance with all Silicon material Tunnel Field Effect Transistor. The two-dimensional (2D) material GNR has been proposed in the channel material to enhance the device performance due to its low bandgap, high mobility, and high saturation velocity. The proposed device's DC, RF, and circuit-level performance analysis has been carried out for the first time. GNR-based channel VTFET shows a better average subthreshold swing (SSAVG) of 16 mV/decade compared to Silicon Vertical Tunnel FET (36 mV/decade) at a drain voltage VDS = 0.5 V. The study of temperature effects on the DC parameters is also included along with the analog/RF FOMs for the proposed two structures. In addition, the performances are compared with other reported works; it is observed that DG-GNR-DMG-VTFET offers better results than Silicon (Si)-based VTFET and other said TFET work. Finally, circuit-level analysis has been done by designing inverter and ring oscillator circuits for the proposed structures, and performance is compared in these two devices. The market-available Silvaco ATLAS TCAD simulator has been used for device-level simulation. Further, circuit-level analysis has been carried out in the Cadence Virtuoso tool using a look-up table-based Verilog-A model.

GaAs-on-insulator based vertical heterojunction tunnel FET: proposal and analysis for VLSI circuit applications

This work analyses the Gallium Arsenide (GaAs)-on-insulator based vertical heterojunction tunnel FET with Gallium Antimonide (GaSb) as source material and GaAs as channel/drain material (GaSb/GaAs VTFET) to enhance the performance of the device and is compared with the Silicon-based VTFET. Silvaco Atlas TCAD tool is employed to perform numerical calculations. Tentative fabrication process flow of GaSb/GaAs VTFET is presented. GaSb is a low bandgap material that enhances the tunneling of charge carriers at source-channel heterojunction. GaSb/GaAs VTFET device outperforms Si-based VTFET in terms of electrical performance metrics such as ON-state current (ION), and ION/IOFF increases by a factor of 11 and 270 respectively; whereas OFF-state current (IOFF), subthreshold swing (SS), threshold voltage (VT) and drain-induced barrier lowering (DIBL) reduce by 95.98%, 39.36%, 17.14% and 29.17% respectively. Further, analog/RF and linearity/distortion performance analysis is carried out. GaSb/GaAs VTFET has improved analog/RF performances in terms of cut-off frequency (fT), gain-bandwidth product (GBP), transit time (τ), device efficiency (DE), transconductance frequency product (TFP) and suppressed distortions in compare to Si-based VTFET. Finally, GaSb/GaAs VTFET is evaluated for process variations and designing digital inverter and common source amplifier circuits. The Look-up-table (LUT) based Verilog-A model within the CADENCE tool has been employed to scrutinize the transient responses of inverter and common source amplifier circuits. Unity gain frequency and 3-dB bandwidth obtained for GaSb/GaAs VTFET amplifier are 15 GHz and 5.97 GHz. Therefore, this work presents GaSb/GaAs VTFET’s strong candidature for analog and digital VLSI circuit designing.

Compact photonic model based on coupled-mode theory for nonlinear interactions in electronic-photonic co-simulation.

This paper demonstrates a Verilog-A compact photonic model based on coupled-mode theory for nonlinear interactions, including four-wave mixing (FWM) and cross-phase modulation (XPM), to present a general framework and methodology for modeling nonlinear interactions in electronic-photonic co-simulation. The model is compatible with existing electronic design automation (EDA) platforms and can support rapid electronic-photonic co-simulation. It avoids describing the complicated physical process of the FWM and provides an easy way for system designers to monitor the dynamics of the critical optical parameters, thus accelerating the co-design and co-optimization of the electronic-photonic hybrid systems incorporating FWM. Meanwhile, the model is not tailored for a particular photonic device but can be applied to different photonic devices as a fundamental component. The model framework and modeling methodology presented in this paper are expected to be further applied to the modeling of other optical nonlinear interactions. The simulation results of the proposed model agree well with both numerical and experimental results. A closed-loop electronic-photonic co-simulation example using the proposed model is also carried out successfully.

A Verilog-A Model for a Light-Activated Semiconductor Gas Sensor

A Verilog-A Model for a Light-Activated Semiconductor Gas Sensor

Design and simulation of artificial retinal stimulation IC with switched capacitor using Si nanowire optical properties.

This study introduces an approach for converting the current from a sensor into controllable voltage. To this end, a switched-capacitor structure was integrated to provide efficient current-to-voltage conversion. The generated voltage was further regulated by an operational amplifier current source, enhancing stability and precision. An n-type metal oxide semiconductor field-effect transistor structure under an H-bridge was integrated into the system to achieve fine-tuned control over current stimulation. This component contributed to voltage regulation and enabled bi-directional control of current flow, offering versatility in adjusting current amplitudes using working and counter electrodes. This dynamic control mechanism was pivotal for effectively controlling the intensity of current stimulation. We applied Verilog-A modeling to simulate the optical characteristics of Si nanowires. The proposed system efficiently converted sensor-derived current into voltage using a switched-capacitor structure. Simultaneously, the precision was enhanced via operational amplifier regulation and n-type metal-oxide-semiconductor field-effect transistor-based H-bridge control. The simulation showed a current stimulus amplitude ranging from 2 to 13 μA for a variable photocurrent of Si nanowires (Rex: 10 kΩ, pulse: 100 Hz, 1 ms). The ability to finely control current stimulation intensity holds promise for diverse applications requiring accurate and adjustable current manipulation. This study contributes to the growing field of sensor technology by offering a unique perspective on the integration of nanostructures and electronic components for an enhanced control and functionality.

Low-power and area-efficient memristor based non-volatile D latch and flip-flop: Design and analysis.

In recent years, non-volatile memory elements have become highly appealing for memory applications to implement a new class of storage memory that could replace flash memories in sequential logic applications, with features such as compactness, low power, fast processing speed, high endurance, and retention. The memristor is one such non-volatile element that fits the fundamental blocks of sequential logic circuits, the latch and flip-flop; hence, in this article, a non-volatile latch architecture using memristor ratioed logic (MRL) inverter and CMOS components is focused, with an additional memristor as a memory element. A Verilog-A model was used to create the memristor element. The simulation findings validated the compact, low-voltage, and reliable design of the latch design. We evolved in technology enough to create a master-slave flip-flop and arrange it to function as a counter and a shift register. Power, number of elements, cell size, energy, programming time, and robustness are compared to comparable non-volatile topologies. The proposed non-volatile latch proves non-volatility and can store data with a 24% reduction in power consumption and a near 10% reduction in area.

Accurate time-domain and frequency-domain co-simulation approach for OEICs design with Verilog-A.

Optoelectronic integrated circuits (OEICs) have enhanced integration and communication capabilities in various applications. With the continued increase in complexity and scale, the need for an accurate and efficient simulation environment compatible with photonics and electronics becomes paramount. This paper introduces a method using the Verilog-A hardware language in the electronic design automation (EDA) platform to create equivalent circuit and compact models for photonic devices, considering their dispersion, polarization, multimode, and bidirectional transmission characteristics. These models can be co-simulated alongside electrical components in the electronic simulator, covering both the time and frequency domains simultaneously. Model parameters can be modified at any stage of the design process. Using the full link of an optoelectronic transceiver as an example, analyses from our Verilog-A model system show a mean absolute percentage error of 1.55% in the time-domain and 0.0318% in the frequency-domain when compared to the commercial co-simulation system (e.g., Virtuoso-INTERCONNECT). This underscores the accuracy and efficiency of our approach in OEICs design. By adopting this method, designers are enabled to conduct both electrical-specific and photonic-specific circuit analyses, as well as perform optoelectronic co-simulation within a unified platform seamlessly.

High speed ultra-low-lower lulse-triggered JLFET Flip-Flop

Power efficiency and enhancing the speed are two major challenges of traditional D-Flip-Flops (D-FF) for designing energy-efficient IOT (internet of thing) devices. Therefore, the main objective of this research article is to design low power high speed D-FF circuits using emerging nanoscale devices. Hence, the first time, in this paper, a pulse-triggered Junctionless D-Flip-Flop (JLFET D-FF) circuit is presented using 15 nm technology, targeting both power budget and high performance concerns. Here, the D-FF circuit uses a signal feedthrough approach to minimize transition duration when output switches from 0 to 1, which requires only a single JLFET structure. Further, to minimize the delay time for the 1 to 0 transition, the discharging path is optimized by employing only two JLFETs. The novel JLFET D-FF circuit is simulated in the Cadence virtuoso simulator using the Verilog-A model. The simulated results have shown that the average power consumption and delay of the proposed circuit are significantly improved as compared to the earlier reported work. The average power consumption in JLFET D-FF for 25% data switching activity is improved by approximately 56% and 64% than ULPFF and SFT-FF, respectively. Further, the power delay performance (PDP) of JLFET D-FF is improved by 96% and 97% at the same data switching activity as compared to ULPFF and SFT-FF, respectively. The performance of the novel D-FF circuit is measured by considering D to Q delay as key parameter which is improved by 77% and 77.5% than ULPFF and SFT-FF, respectively. The simulation results of this work can give insights into the in-circuit behavior of modern semiconductor devices.

A 2-D-Material FET Verilog-A Model for Analog Neuromorphic Circuit Design

A 2-D-Material FET Verilog-A Model for Analog Neuromorphic Circuit Design

Voltage-controlled magnetic anisotropy based physical unclonable function

We design a spintronic physical unclonable function (PUF) based on sub-100 nm voltage-controlled magnetic anisotropy hybrid magnetic tunnel junctions (VCMA-MTJs). This complementary metal-oxide-semiconductor VCMA-MTJ (CMOS/VCMA-MTJ) PUF architecture was evaluated by combining micromagnetic simulations, Verilog-A modeling, and circuit-level simulations. The PUF architecture, comprising four 16 rows × 16 columns arrays, demonstrates effective read and write operations using conventional voltage sensing that are orders of magnitudes lower than previous spintronic-based PUFs. This study proves the potential of the proposed solution in security applications based on hardware authentication.

A Physics-Informed Recurrent Neural Network for RRAM Modeling

Extracting behavioral models of RRAM devices is challenging due to their unique “memory” behaviors and rapid developments, for which well-established modeling frameworks and systematic parameter extraction processes are not available. In this work, we propose a physics-informed recurrent neural network (PiRNN) methodology to generate behavioral models of RRAM devices from practical measurement/simulation data. The proposed framework can faithfully capture the evolution of internal state and its impacts on the output. A series of modifications informed by the RRAM device physics are proposed to enhance the modeling capabilities. The integration strategy of Verilog-A equivalent circuits, is also developed for compatibility with existing general-purpose circuit simulators. The Verilog-A model can be easily adopted into the SPICE-type simulator for the circuit design with a variable step that differs from the training process. Numerical experiments with real RRAM devices data demonstrate the feasibility and advantages of the proposed methodology.

Low Energy and Write-Efficient Spin-Orbit Torque-Based Triple-Level Cell MRAM

Multi-level cell (MLC) is an attractive method to increase the memory storage density and reduce the cost per bit. Write disturb rate (WDR) and large writing step counts are the main challenge to implementing MLCs. In this paper, a three-bit spin-orbit torque magnetic random-access memory (SOT-MRAM) based MLC structure named TLC is proposed. The majority of the bits in TLC require two steps of writing for storage, and the cell exhibits WDR less than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-8</sup> . The performance evaluation of the proposed structure is done on the SPICE framework utilizing a Verilog-A model for the structure. The proposed TLC device is 96% and 92% more energy efficient than spin transfer torque (STT) based TLC and STT/SOT-based TLC structures, respectively. The worst-case write latency of the proposed TLC is 2ns that shows 88% improvement compared to the recently published STT/SOT-based TLC-MRAM. The variability analysis performed using Monte Carlo simulations shows sufficient margins between various writing currents employed for switching the stacked magnetic tunnel junctions (MTJs) that signifies the reliable switching of the different bits in the TLC.

Verilog-A модель эффекта вымораживания примеси в LDD областях при криогенных температурах

The article shows the practical implementation of the impurity freeze-out effect in the lightly-doped areas of the drain and source (LDD) in the Verilog-A model of the resistor. This model is based on a theoretical understanding of the freeze-out effect at cryogenic temperatures and data from the TCAD simulation of a MOSFET. The TCAD simulation data were represented by transconductance characteristics of n- and p-channel transistors Id(Vg) in linear mode (Vd=0.1 V) at temperature range from -200 °C to 27 °C for transistors with dimensions 10 um × 10 um. The model is applicable to the use as part of a macromodel of a MOSFET transistor for a CMOS bulk process with a supply voltage of 1.8 V and a minimum channel length of 0.18 um. Since the model is based on a limited set of TCAD modeling data, this version is the basis on which it is possible to build a geometrically scalable model that will be valid over the entire range of drain voltages.

Behavioral and Electrical Modeling of a 0.5-V Third-Order Continuous-Time Sigma-Delta Modulator with FIR DAC for Audio Applications

Most mobile and wearable devices present digital audio signal processing capabilities. Since the nature of audio signals is analog, there is a need to use analog-to-digital converters (ADCs) with high-resolution for a high signal-to-noise ratio audio acquisition. This paper presents the high-level modeling and design of a continuous-time third-order sigma-delta modulator (CT-SDM) with an FIR DAC for audio devices, using a supply voltage of 0.5 V. The design is divided in three steps and is carried out using the Delta-sigma toolbox and a discrete-time to continuous-time (DT-CT) transformation. First, the schematic implementation with verilogA models is done to estimate the first-integrator amplifier specifications for the modulator to provide 14 bits of ENOB. Following, a two-stage inverter-based amplifier is designed and used to verify the design strategy. Finally, a transistor-level implementation of OTAs and comparator is done to evaluate the CT-SDM performance. An in-depth analysis and discussion are presented to explain the achieved results with those transistor-level circuits.

A Computationally Efficient Compact Model for Ferroelectric Switching With Asymmetric Nonperiodic Input Signals

In this paper, we develop a Verilog-A implementable compact model for the dynamic switching of ferroelectric FinFETs (Fe-FinFETs) for asymmetric non-periodic input signals. We use the multi-domain Preisach Model to capture the saturated P-E loop of the ferroelectric capacitors. In addition to the saturation loop, we model the history dependent minor loop paths in the P-E by tracing input signals’ turning points. To capture the input signals’ turning points, we propose an RC circuit based approach in this work. We calibrate our proposed model with the experimental data, and it accurately captures the history effect and minor loop paths of the ferroelectric capacitor. Furthermore, the elimination of storage of each turning point makes the proposed model computationally efficient compared with the previous implementations. We also demonstrate the unique electrical characteristics of Fe-FinFETs by integrating the developed compact model of Fe-Cap with the BSIM-CMG model of the 7nm FinFET.

Bistable Josephson Junction-Based True Random Number Generator Without Inductors

True random number generators are essential for many applications including security and statistical simulations. A novel superconductive true random number generator is proposed based on inductor-less bistable Josephson junction circuits. The recently proposed design methodology, based on all-Josephson junctions, promises higher area efficiency and simpler circuit design. In this study, this methodology is extended to a superconductive circuit design that extracts randomness from thermal noise present in electronic circuits. A high throughput of 16 GHz is achieved using the proposed design, with no bias or correlation in the output sequence. The quality of the generated randomness is assessed using NIST SP 800-22 statistical tests. A 100 Mb binary sequence is demonstrated to pass all 15 statistical tests using recommended parameters as per NIST guidelines. The simulation methodology, described in detail, is based on the MIT-LL SFQ5EE 10 kA/cm Nb standard process and open source Verilog-A model.

A CNTFET Based Bit-Line Powered Stable SRAM Design for Low Power Applications

Higher charge mobility, gate control, and better electrostatics are the key reasons that make carbon nanotube field effect transistor (CNTFET) a better candidate to become the successor of conventional CMOS transistors. However, the increased charge mobility also enhances the leakage power. This work uses CNTFET for designing a low-power eight-transistor static random access memory (8T SRAM) cell. The leakage power of the proposed cell is reduced by 2.21×compared to conventional 6T SRAM at 0.3V with similar CNTFET parameters. The read and write power delay product of the proposed design is improved by 1.02×and 1.85×, respectively. Moreover, the read/ write/ hold static noise margin of the proposed cell is also enhanced by 1.98×/ 0.99×/ 1.01×, respectively, compared to the conventional 6T design. The proposed cell is also compared with three already proposed CNTFET based 8T SRAM designs. Cadence Virtuoso simulation tool and Stanford University 32 nm CNTFET verilog-A model file are used to achieve simulation results.

An accurate Verilog-A based model for MEMS capacitive accelerometer

This paper presents an accurate macro model for a capacitive micro accelerometer using Verilog-A tool. For this purpose, first the accelerometer is simulated in COMSOL software. Then, considering the simplified physics of the accelerometer, a preliminary Verilog-A model is derived, which is not accurate enough. This initial model has been modified by using mathematical tools and adapting to the results of COMSOL. Furthermore, a switched-capacitor based capacitance to voltage converter (CVC) is used as a readout circuit to validate the proposed model. The CVC is designed, simulated and optimized in the Cadence software by using a 65 nm CMOS technology. In order to reduce low-frequency non-idealities such as flicker noise and DC offsets, a chopper-stabilization technique is used. The power consumption for a 1.2 V supply is 140 μW. Simulation results show a good agreement between COMSOL results and simulation of the proposed model in the Cadence.

Impact of Scaling on Nanosheet FET and CMOS Circuit Applications

In this paper, the impact of scaling on the gate all around the nanosheet field effect transistor (GAA NSFET) is assessed in detail at sub-5-nm nodes for digital and analog/RF applications. The gate length (LG) is downscaled from 20 nm to 5 nm to analyse the various DC and analog/RF performance metrics by fixing the remaining device design parameters. When LG is downscaled from 20 nm to 5 nm, I ON is improved by 2.1×, I OFF increases by three orders in magnitude, SS increases by 27%, DIBL is increased by 4×, and a Vth roll off of 41 mV is noticed. Further, an enhancement of 3.65× was noticed in cut-off frequency (f T) with downscaling of LG from 20 nm to 5 nm. On top of that, the circuit level performance is analysed with LG scaling. The lookup table based Verilog-A model is used in the Cadence Virtuoso tool to demonstrate the circuit performance. The CMOS inverter and ring oscillator’s performance was studied in detail with LG scaling. With LG scaling from 20 nm to 5 nm, the inverter performance metrics like switching current (I SC) is increased by 3.87×, propagation delay (τP), energy delay product (EDP) and power delay product (PDP) are reduced by 65%, 5.5× and 1.95× respectively. Moreover, the ring oscillator offers superior performance with an oscillation frequency (f OSC) of 98.05 GHz when LG is scaled to 5 nm, which is 157% more than f OSC at LG of 20 nm. Thus, with downscaling DC performance degraded due to the SCEs. However, the RF performance of the device improved with downscaling of LG towards lower nodes. Thus, the analyses reveal the scaling capability of NSFET at both device and circuit levels for sub-5-nm nodes.

Design-Oriented Physical Model of Ion-Sensitive Field Effect Transistor for pH Sensing

In this work, we present a circuit design-oriented physical model of the ion-sensitive field-effect transistor (ISFET) for pH-sensing applications. Particularly, this model considers the site-binding interactions at the interface of the electrolyte and the insulator and utilizes a charge-based approach to analyze the field-effect device. The light numerical solution based on the Newton–Raphson–Jacobian method is obtained and validated with experimental results. A semianalytical Verilog-A model is developed by proper selection of initial value and truncating the number of iterations in the numerical method. It follows the numerical results in all regions of operation with a relative error of 2% and a much faster simulation time. The model has a few calibration parameters extracted to fit two experimental devices, including a p-type silicon-on-insulator (SOI) nanowire and conventional n-type ISFET devices. These results suggest that the proposed model is a promising candidate for the circuit-level simulation of ISFET.