Verilog-A Model Research Articles

High speed area efficient 5-bit hybrid Flash ADC using spin devices and CMOS

This paper uses current induced domain wall motion in a magnetic stripe and pre-charge sense amplifiers (PCSA) to design a high speed comparator of a magnetic flash ADC. Current-induced domain-wall (DW) motion is a prominent switching mechanism promising, high-density and high-speed circuits. Domain-wall motion in a magnetic stripe based magnetic flash ADC (Analog to Digital Converter) is area efficient and faster compared to other ADCs. Our proposed 5-bit Flash ADC can operate at 500MS/s with power consumption of 10.5mW. The power consumption can be further reduced to 5.06mW by choosing a smaller step size of 10mV. By using MTJ and domain wall motion in a magnetic stripe with PCSA, SPICE compatible Verilog-A model and CMOS 45nm design kit, its performance such as power and delay have been simulated and compared with other ADCs.

A Novel Refreshment Circuit for 2T1M Neuromorphic Synapse

Neuromorphic systems are the future computing systems to overcome the von Neumann’s power consumption and latency wall between memory and processing units. The two main components of any neuromorphic computing system are neurons and synapses. Synapses carry the weight of the system to be multiplied by the neuromorphic attributes, which represent the features of the task to be solved. Memristor (memoryresistor) is the most suitable circuit element to act as a synapse. Its ability to store, update and do matrix multiplication in nanoscale die area makes it very useful in neuromorphic synapses. One of the most popular memristor synapse configurations is the two-transistor–one-memristor (2T1M) synapse. This configuration is very useful in neuromorphic synapses for its ability to control reading and updating the weight on a chip by signals. The main problem with this synapse is that the reading operation is destructive, which results in changing the stored weight value. In this paper, a novel refreshment circuit is proposed to restore the correct weight in case of any destructive reading operations. The circuit makes a small interrupt time during operation without disconnecting the memristor, which makes the circuit very practical. The circuit has been simulated by using hardware-calibrated CMOS TSMC 130[Formula: see text]nm technology on Cadence Virtuoso and linear ion drift memristor Verilog-A model. The proposed circuit achieves the refreshment task accurately for several error types. It is used to refresh 2T1M synapse with any destructive reading signal shape.

Experimental study of the series resistance effect and its impact on the compact modeling of the conduction characteristics of HfO2-based resistive switching memories

The relevance of the intrinsic series resistance effect in the context of resistive random access memory (RRAM) compact modeling is investigated. This resistance notably affects the conduction characteristic of resistive switching memories so that it becomes an essential factor to consider when fitting experimental data, especially those coming from devices exhibiting the so-called snapback and snapforward effects. A thorough description of the resistance value extraction procedure and an analysis of the connection of this value with the set and reset transition voltages in HfO2-based valence change memories are presented. Furthermore, in order to illustrate the importance of this feature in the shape of the I–V curve, the Stanford model for RRAM devices is enhanced by incorporating the series resistance as an additional parameter in the Verilog-A model script.

Behavioral Model of Silicon Photo-Multipliers Suitable for Transistor-Level Circuit Simulation

Silicon Photomultipliers (SiPMs) are photo-electronic devices able to detect single photons and permit the measurement of weak optical signals. Single-photon detection is accomplished through high-performance read-out front-end electronics whose design needs accurate modeling of the photomultiplier device. In the past, a useful model was developed, but it is limited to the device electrical characteristic and its parameter extraction procedure requires several measurement steps. A new silicon photomultiplier model is proposed in this paper. It exploits the Verilog-a behavioral language and is appropriate to transistor-level circuit simulations. The photon detection of a single cell is modeled using the traditional electrical model. A statistical model is included to describe the silicon photomultiplier noise caused by dark-count or after-pulsing effects. The paper also includes a procedure for the extraction of the model parameters through measurements. The Verilog-a model and the extraction procedure are validated by comparing simulations to experimental results.

Impact of ion implantation on stacked oxide cylindrical gate junctionless accumulation mode MOSFET: An electrical and circuit level analysis

This article analyses the effect of ion implantation on electrical and circuit-level characteristics of stacked oxide cylindrical gate (CG) junctionless accumulation mode (JAM) MOSFET. Ion implantation and subsequent annealing create a Gaussian type doping profile inside the channel. A detailed study of electrical characteristics such as: drain current, threshold voltage, Ion/Ioff, transconductance (gm), output conductance (gd), capacitances (Cgs, Cgd, Cgg), unit gain frequency (fT), transit time (τ), transconductance frequency product (TFP) and gain bandwidth (GBW) product have been performed. Further, an inverter has been designed with a complimentary p-MOSFET and a lookup table-based Verilog-A model has been generated for the same. Various dc and transient parameters such as noise margin, rise time, fall time propagation delay, voltage overshoot, average current, and power dispassion have been analyzed in detail. Henceforth, a 6 T SRAM cell has been implemented with ion-implanted stacked oxide CG-JAM MOSFET and read margin, write margin, access time and N-curve analysis have been performed. Various figures of merits (FOMs) have also been studied for the device at the circuit level. All the device simulations have been performed using a 3-D TCAD tool from COGENDA. Verilog-A model-based circuit simulations have been done in the Cadence-Virtuoso platform.

Assessment of 2D-FET Based Digital and Analog Circuits on Paper

Two-dimensional (2D) materials represent an emerging technology for transistor electronics in view of their attractive electrical and mechanical properties. This work investigates molybdenum disulfide (MoS2) based field-effect transistors (FETs) fabricated on paper substrate for designing both digital and analog circuits, such as inverter, current mirror, and Physical Unclonable Function (PUF) bitcell. Electrical measurements of fabricated devices are exploited to setup a look-up-table (LUT)-based Verilog-A model to be integrated in a commercial circuit simulator. Obtained results prove the potential of paper-based MoS2 FETs as building blocks of next-generation integrated circuits for a wide range of practical applications.

Effect of Threshold Switching Selectors on One-Selector One-Resistor Crossbar Arrays

In this paper, the influence of selector on the performance of 1S1R crossbar array memory is focused. First, a read-write circuit is designed based on the 1S1R cell model, which is a Verilog-A physical model built by our research team in the former work. Then, the parameters of selector (Vth, Vhold, RS-on, RS-off,NL) with different array sizes are calculated and analyzed. Different from the influence of selector on 1S1R cell, the read/write margin and read/write power consumption of the 1S1R crossbar array are impacted by selector significantly. Selectors with large Vth improve the write margin, but too large Vth reduce the read margin.The ON-resistance of the selector affects the read power consumption more than the OFF-resistance of the selector does, and the larger nonlinearity improves the overall performance of the crossbar array. Finally, this new 1S1R crossbar array memory is compared with 1R crossbar array memory and the result proved that the optimized memory can reduce the leakage current and power consumption to the large extent.

Comprehensive Design Methodology of Switch Stack in Pulsed Power Supply for EML

This article presents a comprehensive methodology for designing a fully protected efficient semiconductor switch stack for electromagnetic launchers (EMLs), using commercially available thyristors and diodes by developing behavioral (Verilog-A) models of the switches accounting for their nonidealities. The appropriate values of protection components are obtained through SPICE simulations. Using ABB thyristors and diodes, a design-example of a 400-kJ pulse-forming network (PFN) with rated peak voltage and peak current of 11 kV and 135 kA, respectively, is presented. The simulated peaks of dv/dt and di/dt of the main switch are found to be well within the maximum permissible limits, 40% and 10% respectively, for a turn-on timing skew of 1 μs between the thyristors. The addition of the protection components reduces the efficiency ( η) of the PFN by 3.5%, thus indicating that proper designing of the protection components does not decrease the efficiency of the PFN significantly. The second example of a 100-kJ PFN using off-the-shelf Infineon switches is also presented to clarify the proposed methodology.

Graphene Nanoribbons Based 5-Bit Digital-to-Analog Converter

McCulloch-Pitts neuron structures are comprised of a number of synaptic inputs and a decision element, called soma. In this paper, we propose a 5-bit Graphene Nanoribbon (GNR)-based DAC to fulfill the role of the summation element featuring programmable input weights. The proposed GNR-based 5-bit DAC relies on: (i) GNR unit current cells and (ii) a GNR logic thermometric decoding block. Our implementation is based on mapping the GNR structure's conductance using Matlab and performing the required SPICE analysis using the Matlab based GNR Verilog-A model. The unit current cell geometry and bias conditions were chosen based on the unit cell's conductance map from which we derived its I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> ratio, as well as transfer and output characteristics, resembling the classical MOSFET counterpart. By utilizing GNR devices instead of FinFET counterparts, a reduction of the active area of the 5-bit current DAC by up to a factor of three can be achieved. Furthermore, the GNR implementation achieved this while maintaining comparable INL and DNL performance to that of the FinFET variant, i.e., DNL of [-0.196, 0.088] LSB and INL of [-0.809, 0.364] LSB for the proposed GNR 5-bit DAC while operating at a supply voltage of only 0.2 V.

A Comprehensive Physics-Based Current–Voltage SPICE Compact Model for 2-D-Material-Based Top-Contact Bottom-Gated Schottky-Barrier FETs

In this article, we report the development of a novel physics-based analytical model for explaining the current-voltage relationship in Schottky barrier (SB) 2-D-material field effect transistors (FETs). The model has at its core the calculation of the surface-potential (SP) which is accomplished by invoking 2-D density of states in conjunction with Fermi-Dirac (FD) distribution for electron and hole statistics. The explicit computation for the SP, carried out using the Lambert-W function together with Halley's method, is used to construct the SP-based band-diagram for realizing the transparency of the SBs. Thereafter, the ambipolar current is derived in terms of the electron and hole injection phenomena-the thermionic emission and Fowler-Nordheim tunneling mechanisms-at the SB contacts. Furthermore, drift-diffusion current is derived in terms of the SP and incorporated in the model to account for the scattering in the intrinsic 2-D channel. Finally, the Verilog-A model is validated against experimental I-V data reported in the literature for two different 2-D-material systems. This is the first demonstration of an explicit SP-based SPICE model for ambipolar SB-2-D-FETs that is simultaneously built on tunneling-emission and drift-diffusion formalisms.

An Ultra-low-power Static Random-Access Memory Cell Using Tunneling Field Effect Transistor

In this research article, an Ultra-low-power 1-bit SRAM cell is introduced using Tunneling Field Effect Transistor (TFET). This paper investigates feasible 6T SRAM configurations on improved N-type and P-type TFETs integrated on both InAs (Homojunction) and GaSb-InAs (Heterojunction) platforms. The voltage transfer characteristics and basic parameters of both Homo and Heterojunctions are examined and compared. The proposed TFET based SRAM enhances the stability in the hold, read, and write operations. This work evaluates the potential of TFET which can replace MOSFET due to the improved performance with low-power consumption, high speed, low sub-threshold slope, and supply voltage (VDD = 0.2 V). The results are correlated with CMOS 32nm technology. The proposed SRAM TFET cell is implemented using 30nm technology and simulated using an H-SPICE simulator with the help of Verilog-A models. The proposed SRAM TFET cell architecture achieves low power dissipation and attains high performance as compared to the CMOS and FINFET.

Design, Analysis and Application of Embedded Resistive RAM Based Strong Arbiter PUF

Resistive Random Access Memory (RRAM) based Physical Unclonable Function (PUF) designs exploit either the probabilistic switching or the resistance variability during forming, SET and RESET processes of RRAM. Memory PUFs using RRAM are typically weak PUFs due to fewer number of challenge response pairs. We propose a strong arbiter PUF based on 1T-1R bit cell which is designed from conventional RRAM memory array with minimally invasive changes. Conventional voltage sense amplifier is repurposed to act like an arbiter and generate the response. Similarly, address and data lines are repurposed to act as challenge and response bits respectively. The PUF is simulated using 65 nm predictive technology models for CMOS and Verilog-A model for a hafnium oxide based RRAM. The proposed PUF architecture is evaluated for uniqueness, uniformity and reliability for various number of stages. It demonstrates mean intra-die Hamming Distance (HD) of 0.135 percent and inter-die HD of 51.4 percent, and passes the NIST tests. We study the vulnerability of proposed PUF to machine learning attacks. We also present an application of proposed PUF for data attestation in the internet of things. Proposed PUF-based data attestation consumes 9.88pJ of total energy per data block of 64-bits and offers a speed of 120.7 kbps.

An efficient macro model for CMOS-MEMS thermal wind speed sensor

In this paper, we propose a thermal wind speed sensor Verilog-A model with thermal-fluid-electric hybrid characteristics. Because the structure of the thermal wind sensor and the interface circuit chip are designed separately, which cannot effectively carry out MEMS-IC (integrated circuit) co-simulation, the overall performance of the sensor and interface circuit chip is prone to large deviation. At the same time, the separation of MEMS structure and IC design process leads to long product development cycle and high cost. This paper proposes an improved simulation model by analyzing the behavior characteristics of the thermal wind speed sensor. The simulation model consists of 11 thermistors, 3 capacitors, a voltage-controlled voltage source, and a voltage-controlled current source. The Taylor series expansion of the differential equation of heat conduction is carried out, and then the thermistor and capacitor networks are established according to the corresponding relationship between the thermal parameters and the electrical parameters, including the thermal conduction unit, the convection unit and the heat capacity in the chip. The model fully considers the effects of various physical effects and parasitic effects, and is implemented using the hardware description language Verilog-A. The sensor and interface circuit can be simulated simultaneously to optimize the circuit design. It is beneficial to the integration of sensors and interface circuit, reducing the number of tape-outs, increasing the success rate, and reducing costs. The consistency between the simulation results and the experimental curves verified the correctness of the macro model. The behavior characteristics of constant power (CP) and constant temperature heating were described. In CP mode, the output voltage error is less than ± 6.5%, the chip temperature error is less than 4.0%. The presented modeling approach can be the basis for the development of complete MEMS-IC design technology library of thermal wind speed sensor, aiming at optimum designs of integrated thermal wind speed sensor.

Single and double‐gate based AlGaN/GaN MOS‐HEMTs for the design of low‐noise amplifiers: a comparative study

In this study, a 60 nm gate length double-gate AlGaN/GaN/AlGaN metal-oxide-semiconductor high-electron-mobility transistor (MOS-HEMT) is proposed and different electrical characteristics, such as DC, small-signal, radio-frequency (RF) and high-frequency noise performances of the devices are characterised through TCAD device simulations. The results of double-gate MOS-HEMT are compared with the TCAD simulation results as well as with available experimental data of single-gate AlGaN/GaN MOS-HEMT having a similar gate length available from the literature. It is observed that the double-gate AlGaN/GaN/AlGaN MOS-HEMT shows good sub-threshold slope, improved ON current, short-channel effect immunity, improved RF and noise performance. A look-up table-based Verilog-A model is developed for both devices and the models are incorporated into the Cadence EDA tool to utilise the proposed device in circuit simulations. The Verilog-A model is applied to design a 1–20 GHz wideband feedback cascode low-noise amplifier (LNA). Performance variability of LNA due to single- and double-gate MOS-HEMT is also investigated.

Flicker Noise Formulations in Compact Models

This article shows how to properly define modulated flicker noise in Verilog-A compact models, and how a simulator should handle flicker noise for periodic and transient analyses. By considering flicker noise in a simple linear resistor driven by a sinusoidal source, we demonstrate that the absolute value formulation used in most existing Verilog-A flicker noise models is incorrect when the bias applied to the resistor changes sign. Our new method for definition overcomes this problem, in the resistor as well as more sophisticated devices. The generalization of our approach should be adopted for flicker noise, replacing the formulation in existing Verilog-A device models, and it should be used in all new models. Since Verilog-A is the de facto standard language for compact modeling, it is critical that model developers use the correct formulation.

Study of analog performance of common source amplifier using rectangular core–shell based double gate junctionless transistor

A new state of the art double gate junctionless transistor (DGJLT) namely the rectangular core–shell DGJLT (RCS-DGJLT) based common source amplifier circuit is designed to investigate the performance. An RCS-DGJLT device is designed using a visual technology computer aided design tool and look up table-based Verilog-A model has been designed to carry out spice simulation of the circuit. Device simulation of RCS-DGJLT shows the extraordinary performance when compared to conventional DGJLT. The RCS-DGJLT exhibits an OFF current (Ioff ) ∼10−14 A, ON current (Ion ) ∼10−5 A, ON/OFF current ratio (Ion /Ioff ) ∼109, subthreshold slope ∼68.9 mV decade−1 and drain induced barrier lowering ∼52.6 mV V−1. Also, the AC response of RCS-DGJLT exhibits good performance like lower miller capacitances of order 10–16 F, maximum unity gain frequency of 138.8 GHz, transconductance generation efficiency of 40 V−1, and gain-bandwidth product of 25.4 GHz. The common source amplifier circuit using RCS-DGJLT provides the amplification up to 3.3 times which implies gain (Av ) to be 3.3. The low leakage power of 10.4 pW and average power of 31.2 µW of common source amplifier circuit based on RCS-DGJLT shows the greater potential of using the proposed device in analog applications. Also, the complete flow chart of the process used to design an analog circuit based on proposed RCS-DGJLT is discussed. The result shows the potential of using the RCS-DGJLT device in designing high-frequency applications.

Impact of heterogeneous gate dielectric on DC, RF and circuit-level performance of source-pocket engineered Ge/Si heterojunction vertical TFET

This paper reports the DC, RF and circuit-level performance analysis of short-channel Ge/Si based source-pocket engineered (SPE) vertical heterojunction tunnel field effect transistors (Ge/Si SPE-V-HTFETs) with and without a heterogeneous gate dielectric (HGD) structure for the first time. The DC performance parameters in terms of ION/IOFF and subthreshold swing (SS) are investigated for the proposed V-HTFETs. The average SS for the proposed V-HTFET with an HGD is found to be as low as 20 mV dec−1 compared to V-HTFET without any HGD (26 mV dec−1) at VDS = 0.5 V. The proposed Ge/Si SPE-V-HTFET with an HGD possesses higher cut-off frequency of 502 GHz and maximum frequency of oscillation of 2.33 THz at VDS = 0.5 V over the Ge/Si SPE-V-HTFET without any HGD which possesses cut-off frequency of 273 GHz and maximum frequency of oscillation of 1.47 THz. The proposed Ge/Si SPE-V-HTFET with and without an HGD have then been used for designing a basic current mirror circuit. Device-level study has been carried out using SILVACO ATLASTM TCAD simulator while the circuit-level investigation has been performed using the look up table based Verilog-A models in the CADENCE Virtuoso tool. The performances of the Ge/Si SPE-V-HTFET with HGD based current mirror circuit is observed to be better than the corresponding current mirror circuit designed by Ge/Si SPE-V-HTFET without any HGD.

A high-efficiency piezoelectric-based integrated power supply for low-power platforms

In this paper, a high-efficiency piezoelectric-based integrated power supply (PEPS) is proposed. The proposed PEPS supplies low-power platforms (i.e., Passive infrared sensor) with 51.4% power conversion efficiency (PCE). The piezoelectric transducer designing and modeling are developed using COMSOL. Furthermore, a Verilog-A model is presented to be integrated with the proposed power management unit where the output DC supply is 3.3 V. Finally, a prototype of the proposed PEPS is implemented using UMC 0.13 μm CMOS technology, the design occupies approximately 0.092 mm2.

A New One-selector One-resistor Verilog-A model for Circuit Simulsation

In this paper, a compact model of one-threshold switching selector (1S) one-bipolar resistive random-access memory (1R) is developed for 3D memory circuit simulation. Firstly, the mathematical formulas are presented to describe the two different states before and after the threshold switching for S. The formulas are expressed in Verilog-A to develop a S compact model. Secondly, the parameters (Vth1, Vth2, Vop, α, β, Rs) in the S model are adjusted to match with R. Especially, Vth1 and Vth2 can be adjusted according to the set and the reset voltages of R. Lastly, simulations are conducted in 7T1R circuit and cross-point array performance of the new 1S1R Verilog-A model is analyzed to validate the model performance.

Device and Circuit-Level Assessment of GaSb/Si Heterojunction Vertical Tunnel-FET for Low-Power Applications

This article investigates the performance of a vertically grown GaSb/Si tunnel field effect transistor (V-TFET) with a source pocket to enhance the performance of the device. The commercially available Silvaco TCAD has been used for simulating the proposed V-TFET structure. A low bandgap material, GaSb, is used in the source region for the first time to enhance the carrier tunneling through the source (GaSb)-channel (Si) heterojunction. The proposed V-TFET with a pocket shows the improved subthreshold swing (SS) of 26 mV/decade at ${V}_{{\textit {DS}}}= 0.5$ V over the V-TFET without any pocket. The effects of temperature on SS and ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio along with the analog/RF figures of merit (FOMs) are also analyzed for V-TFETs with and without a pocket. The results are also compared with some recently reported TFETs. The dc and analog/RF performances of V-TFET with a pocket are shown to be better than those of the V-TFET without a pocket and other reported TFET structures. Finally, the applications of V-TFETs with and without a pocket in designing inverter and ring oscillator circuits have been demonstrated. The dc and transient responses of the V-FET-based inverter and ring oscillator circuits have been analyzed using the Verilog-A model in the CADENCE tool.