Verilog Hardware Description Language Research Articles

An Advanced Hardware Implementation of the Trial Division Algorithm for Dividers Utilizing RISC-V ISA

In this paper, we try to design a divider based on RISC-V instruction set architecture (ISA). Since the hardware design of the divider in the ALU is very important for the CPU to implement the arithmetic function. In view of the advantages of the trial division method in the division algorithm and the popularity of the RISC-V ISA, this paper attempts to design a trial division divider utilizing the RISC-V ISA. In this design, the principle of trial division, flow chart, state diagram, RISC-V instructions of division, whole divider module and logic will be designed in detail. To test the function and feasibility, the hardware description is carried out in the Verilog hardware description language (HDL). In this description, four division RISC-V instructions are integrated. Modelsim is used to verify and test the functionality of the divider. The test waveform is used as a result to verify the feasibility of the divider.

Design and Implementation of a Synchronous AHB to APB Bridge in System-on-Chip Applications

The requirement of effectively combining key units in an integrated system is proliferating. SoC system is developed to provide a chip-level integration, which become the inevitable trend of integrated circuit development and is widely used in smartphones, industrial applications, and microcontrollers. The ARM AMBA protocol works as a universally adopted way of interaction between various parts of the system. In AMBA architecture, the AHB to APB bridge significantly contributes to combining the high-performance AHB bus and low-power APB bus in the SoC system. This project is to implement an AHB to APB bridge using Verilog, enabling stable data transfer between these two buses. The proposed AHB to APB bridge is intended to fit different read or write strategies and ensure the proper working of the peripherals on the APB bus. The bridge has been implemented via Verilog Hardware description language (HDL). A test bench was created with a virtual AHB host and an optimized SRAM as the high-speed APB peripheral. Verdi simulation shows the bridge completely meets the design intention.

Design and Implementation of Digital Integrated Circuit Based CPU

This paper presents a simplified 16-bit CPU design and its implementation using digital integrated circuits developed with Verilog hardware description language, while emphasizing simulation through the EDA tool. This design puts more emphasis on the critical roles played by the data path and the control unit, executing key instructions including arithmetic operations such as addition, subtraction, bitwise logic, and conditional jumps. This structurally modular CPU is both functioning and stable in nature, allowing support for future enhancements and enhancements as well, thereby serving as an effective model towards an understanding of the principles of CPU design. The execution of these basic instructions puts the core of the CPU under test and reaffirms its proper operation in respect of the detailed instruction set, while its extensibility design confirms further improvement possibilities for future complex instructions as well as finite-state machine optimization for the control unit. The present work not only proves the possibility of creating a fully working CPU, using readily available bare minimum resources to implement a prototype, but is also a breakthrough in future research with CPU architecture. The obtained results will shed light on CPU functionality optimization and extension, being the ground for building more powerful and effective processors in the future.

Hardware-accelerated neural network model for early prediction of sudden cardiac arrest based on heart rate variability metrics

AbstractSudden Cardiac Arrest (SCA) constitutes a dire medical condition, marked by the abrupt cessation of effective blood circulation due to the heart's failure to contract properly. This leads to acute circulatory collapse, often culminating in loss of consciousness within an hour and potentially resulting in fatality within minutes if left unattended. Heart rate variability (HRV) serves as a critical biometric, derived from electrocardiogram (ECG) signals with ventricular depolarization waves to further calculate the R-R Intervals (RRIs). These intervals provide the basis for extracting various characteristics of cardiac rhythm, encompassing time-domain, frequency-domain, and nonlinear features. This study presents a neural network-based classification algorithm that leverages HRV metrics to categorize patients into SCA and Normal Sinus Rhythm (NSR) cohorts. The proposed neural network (NN) model showcased impressive results, achieving an accuracy of 96.23%, a sensitivity of 94.35%, and a specificity of 98.12% in detecting SCA, as evaluated through leave-one-subject-out analysis. In order to harness the benefits of hardware acceleration, the algorithm is implemented on a Field-Programmable Gate Array (FPGA). Its computational efficiency is subsequently benchmarked against traditional software-based methodologies. The hardware-level implementation is made possible in Verilog hardware description language (HDL) and was verified successfully with expected performance by register-transfer level (RTL) simulation via Vivado 2020.2.

An efficient XOR-free implementation of polar encoder for reconfigurable hardware

— This paper presents a novel approach to implementing an XOR-Free architecture of the non-systematic polar encoder (NSPE) for 5G radio. The optimization of XOR logic for hardware (HW) implementation is essential to reduce delay and power consumption. The proposed architecture for NSPE replaces XOR operations with combinational logical patterns, and some redundant patterns are removed with the help of bit manipulation to make it more efficient. The design infers multiplexers (2:1 or 4:1) and inverters as its functional units, making the design adequate and effective in alleviating HW complexity. The XOR-Free encoder performs the same functionality as the XOR-based conventional encoder. We have written a MATLAB script that generates Verilog hardware description language (HDL) code for fully or partially parallel polar encoders tailored to specific code lengths (N) and degrees of parallelism (M). A comparative analysis of various fully and partially parallel encoders with the XOR-Free algorithm is presented. The implementation results show that the proposed architectures are more efficient in terms of HW cost, power consumption, throughput, and latency.

FPGA-Based Numerical Simulation of the Chaotic Synchronization of Chua Circuits

The objective of this work was to design and implement a system based on reconfigurable hardware as a study tool for the synchronization of chaotic circuits. Mathematical models were established for one circuit, two synchronized, and multiple synchronized Chua circuits. An ordinary differential equation solver was developed applying Euler’s method using the Verilog hardware description language and synthesized on a Spartan 3E FPGA (Field-Programmable Gate Array) equipped with a 32-bit RISC processor, 64 MB of DDR SDRAM, and 4 Mb of PROM. With a step size of 0.005 and a total of 10,000 iterations, the state equations for one and three Chua circuits were solved at a time of 0.2 ms and a frequency of 50 Mhz. The logical resources used by the system did not exceed 4%. To verify the operation, a numerical simulation was carried out using the Octave V9.1.0 calculation software on an Intel(R) Core i7-9750H CPU 2.59 GHz computer, obtaining the same results but in a time of 493 ms and 3.177 s for one and three circuits, respectively.

Design and performance analysis of asynchronous network on chip for streaming data transmission on FPGA

The majority of the system on chip (SoC) uses the network on chip (NoC) as routing ports for data transfer from node-to-node with minimal power consumption and low latency and high throughput. This paper concentrates on the ability to model the asynchronous NoCs on the asynchronous circuits on field programmable gate arrays (FPGAs). A 3×3 NoC and its universal asynchronous receiver transmitter (UART) protocol is designed and its simulation of the Verilog hardware description language (VHDL) code is done and tested on the Artix-7 FPGA kit, the testing processes in done using the Chipscope tool. In order to meet target requirements in terms of power consumption and latency, the label switching (LS) technique is used as routing. The proposed LS-NoC with level-encoded dual-rail (LEDR) encoding technique provides throughput by registering the packet between the different routers and it helps to improve throughput and speed. The effectiveness of the data transfer is measured and analyzed through a synthesis summary in terms of lookup table’s (LUT’s), slice registers, flip flops’s (FF’s), latency, and packet delivery ratio (PDR) for the traffic pattern generator. The proposed NoC is designed for 8×8 and each port size is 21 bits including ID’s of source and destination routers. The results can be justified by following results: improvement of LUTs is about 12%, flip-flops are 7%, improvement of throughput is 23% and delay is reduced by 26%.

FPGA in hardware description language based digital clock alarm system with 24-hr format

Currently, digital clock adapts microprocessor or microcontroller system. Performance of speed and reconfigurability issue become a main concern in digital clocks. New additional feature may be introduced in digital clocks in the future. Field programmable gate array (FPGA) offer better performance of speed and reconfiguration features. Based on these advantages, it is essential to study or explore the digital clock with FPGA design. The objective in this study is to create a hardware description language (HDL)- based digital clock with alarm system and implement it onto the Altera DE2- 115 board. Using Verilog HDL language in Quartus Prime 20.1 Lite Edition software, all submodule components is developed and being test benched using ModelSim-Altera Starter Edition 13.1 to ensure the correct functionality. Then all inputs and outputs will be assigned through pin assignment in the software. For verification purpose, it will be downloaded to the Altera DE2-115 board. In conclusion, the file has been successfully implemented to the board and the digital clock with alarm is fully functional as expected. This was proved by the alarm signal, time adjustment and display of the three-display mode which is clock, alarm, and input where each mode carries their own functions as expected.

Optimization research of handwritten digit recognition algorithm based on hardware neural networks

In the modern era of digitization, the widespread application of handwritten numerical data has led to an exponential increase in data volume, necessitating efficient real-time recognition and processing systems. This project is grounded in the foundational structure of neural networks, with a specific focus on integrating these networks into hardware through Very-Large-Scale Integration (VLSI). The primary objective is to achieve faster processing speeds, lower power consumption, and real-time operations. The central emphasis of this study is the design and implementation of a hardware neural network system tailored specifically for handwritten digit recognition. Drawing from neural network theory, we explore the construction of a hardware-based handwritten digit classifier. The fundamental model employed is the single-layer perceptron neuron model. Upon receiving 28x28 pixel grayscale images, the image classifier utilizes pre-trained weights, activation functions, and a maximum selector to compare and output recognition results for numerical digits. The concrete implementation is realized using the Verilog hardware description language, coupled with algorithm optimization strategies to enhance performance and efficiency. This research endeavor aims to provide an effective hardware solution for real-time handwritten digit recognition in the digital age.

AN EFFICIENT VLSI IMPLEMENTATION OF EDGE DETECTION OF IMAGES

Edge detection is a fundamental process in image processing with significant implications across multiple domains. Within the realm of object detection, the accurate delineation of image perimeters forms the bedrock for subsequent analysis. In this study, we present an optimized Laplacian Edge Detection algorithm tailored for efficient implementation in hardware.Leveraging approximation methodologies and strategic pipelining, we streamline complex operations, thereby reducing latency and resource consumption. Our implementation, realized through the Verilog Hardware Description Language (VHDL), stands as a testament to the efficacy of our approach. Through rigorous optimization and meticulous comparison with conventional Sobel edge detection, we demonstrate superior performance metrics, including enhanced Area utilization, reduced Time Delay, and improved Power Efficiency. This work underscores the importance of methodological refinement and technological innovation in advancing edge detection techniques for practical applications. Keywords: Laplacian, Sobel, Kernel, Pixel range, Area, Power

A Versatile Approach for Adaptive Grid Mapping and Grid Flex-Graph Exploration with a Field-Programmable Gate Array-Based Robot Using Hardware Schemes.

Robotic exploration in dynamic and complex environments requires advanced adaptive mapping strategies to ensure accurate representation of the environments. This paper introduces an innovative grid flex-graph exploration (GFGE) algorithm designed for single-robot mapping. This hardware-scheme-based algorithm leverages a combination of quad-grid and graph structures to enhance the efficiency of both local and global mapping implemented on a field-programmable gate array (FPGA). This novel research work involved using sensor fusion to analyze a robot's behavior and flexibility in the presence of static and dynamic objects. A behavior-based grid construction algorithm was proposed for the construction of a quad-grid that represents the occupancy of frontier cells. The selection of the next exploration target in a graph-like structure was proposed using partial reconfiguration-based frontier-graph exploration approaches. The complete exploration method handles the data when updating the local map to optimize the redundant exploration of previously explored nodes. Together, the exploration handles the quadtree-like structure efficiently under dynamic and uncertain conditions with a parallel processing architecture. Integrating several algorithms into indoor robotics was a complex process, and a Xilinx-based partial reconfiguration approach was used to prevent computing difficulties when running many algorithms simultaneously. These algorithms were developed, simulated, and synthesized using the Verilog hardware description language on Zynq SoC. Experiments were carried out utilizing a robot based on a field-programmable gate array (FPGA), and the resource utilization and power consumption of the device were analyzed.

FPGA-Based Speed Control Strategy of PMSM Using Improved Beetle Antennae Search Algorithm

To improve performance in terms of overshoot and motor response speed when a permanent-magnet synchronous motor (PMSM) with a proportional–integral (PI) controller is subjected to external disturbances, this paper proposes a speed control strategy based on an enhanced Beetle Antennae Search algorithm, which allows for adjustable parameters of the PI controller within a certain range. Firstly, to enhance the global and local search capabilities of each individual beetle, the step size was improved by linearly decreasing it. Secondly, a simulation model of a PMSM closed-loop control system was built to verify the effectiveness of the improved Beetle Antennae Search (BAS) algorithm. Finally, a linear feedback shift register model that generates four random numbers was developed on a field-programmable gate array (FPGA). The improved BAS algorithm for the PMSM control system was implemented on an FPGA using the Verilog hardware description language, and the feasibility of the system was verified through hardware simulation. Additionally, the hardware resource consumption on different FPGA platforms was analyzed. The simulation results demonstrate that the proposed new speed control strategy can reduce the overshoot and improve the motor response speed.

Leveraging CRC Error Detection for Enhanced Error Correction in Digital Communication Systems

In this study, CRC error detection techniques will be used to not only identify but fix single-bit errors in digital communication systems. In the past, CRC codes have been employed mainly for their ability to detect errors efficiently. However, this paper suggests a new way that will make it possible to modify CRC functions and thus correct the identified errors. It is intended that by using an optimized look-up table in Verilog hardware description language with an advanced Xilinx 14.7 toolchain, this research can increase the dependability and effectiveness of error correction mechanisms found in digital systems. The study presents how to create a detailed hardware description, optimize lookup tables for minimal resource usage and increased error correction capability; then synthesizes design with Xilinx 14.7.The conclusion makes a practical contribution towards identification and removal of single-bit errors which indicates a turning point in the use of Cyclic Redundancy Check (CRC) technology from being just about error detection to full scale error correction. This enhancement has the potential to greatly increase the durability and reliability of data transmission and storage systems, especially in critical applications requiring utmost data integrity. Keywords: Cyclic Redundancy Check (CRC), Error detection, Single-bit errors, Optimized lookup table, Xilinx 14.7 toolchain.

Energy efficient FPGA implementation of an epileptic seizure detection system using a QDA classifier

Epilepsy is a severe neurological disorder that causes seizures. It is detected by analyzing the electrical impulses of the human brain. Monitoring the brain is commonly done using an electroencephalogram (EEG). Seizure detection from the large recorded EEG dataset is a demanding task. However, numerous machine learning classifiers and the appropriate features can detect seizures. The Hjorth and statistical parameters are used in this study to provide an effective method for field programmable gate array (FPGA) realization of epileptic seizure detectors from EEG signals. Mobility, interquartile range (IQR), median absolute deviation (MAD), energy, non-linear energy, and simple square integral (SSI) are the various features analyzed in this work. The hardware architecture of the seizure detection system is captured in Verilog hardware descriptive language and realized on the Artix-7 FPGA. This paper presents three separate seizure detection models designed by pairing three different features with the Quadratic discriminant analysis (QDA) classifier. Among these three models, the energy and non-linear energy-based seizure detection system offers better performance than existing seizure detection systems because it possesses the lowest dynamic power consumption (0.116 µW), the highest design accuracy (99.4 %), and the highest sensitivity (100 %), which makes it the best seizure detection system for real-time applications.

Advanced VLSI-based digital image contrast enhancement: A novel approach with modified image pixel evaluation logic

This research uses an extremely memory-intensive and power-efficient very-large-scale-integration (VLSI) architecture to perform nonlinear scaling on pictures. Images can be scaled either up or down so that they can be adapted to the differing resolutions of a variety of devices, such as cameras and printers. Photography with a high resolution calls for significantly more storage space and processing power. The branch of image processing known as “image fusion” has recently had a meteoric rise in prominence. The rapidly growing usage of digital imagery in remote sensing and satellite applications has led to an increase in the need to both store and process massive amounts of picture data. This demand has resulted in an increase in the availability of storage space. Traditional fusion methods produce spatial distortions despite their generally high level of spatial performance. Because of this, the discrete wavelet transformation (DWT), currently the most efficient approach for processing images, focuses on finding a solution to this problem. Within the scope of this investigation, we propose the modified image pixel evaluation logic (MIPEL), a functional method for incorporating the lifting-based strategy utilized in DWT-based picture fusion. In order to avoid excessive delays, high-resolution photo processing typically makes use of hardware processing, which necessitates the utilization of more complex apparatus and more time. In this work, the hardware description language verilog is employed to evaluate the effectiveness of various fundamental approaches to the enhancement of pictures. VHDL is a relatively recent method that has replaced more traditional simulations in the process of producing results for signal processing. It does this by allowing rapid access to physical VLSI representations. Utilizing the proposed MIPEL as a starting point, this study aims to design, model, simulate, and develop several different strategies for enhancing photos using FPGA. Because they take place on the pixel level and in the immediate neighborhood of a pixel, the enhancements that may be made to an image can be thought of as point processing procedures. VLSI architecture is developed for contrast augmentation for low-contrast source photos using pixel-based image fusion, and in the simulation results that followed, we offer findings that clearly illustrate the efficiency of this technology.

Implementation of 64-Bit RISC Processor Using Vedic Multiplier

Abstract: In this project, 64 bit RISC processor designed with Vedic multiplier design. Reduced Instruction Set Computer (RISC) is a design which presents better performances, higher speed of operation and favors the smaller and simpler set of instructions. In addition to multiplier which is implemented using vedic mathematics we are also proposing an adder which is mux- based full adders for building higher bit adders in an area and speed efficient which is implemented in addition as well as for compression in vedic mathematic to obtain the output. A 64 bit RISC processor designed in this paper is capable of executing more number of instructions with simple design, using the Verilog Hardware Description Language (HDL) and the design is simulated in the Xilinx Vivado 2018.3. The main achievement in this work is that the multiplier unit in Arithmetic and Logic Unit (ALU) and Multiplier and Accumulator (MAC) is implemented using Vedic Sutras. The main principle used in Vedic mathematics is to reduce the typical calculation of conventional mathematics to very simple one and hence reduce the overall computational complexity. Vedic Multiplier design is based on “Urdhva Triyakbhyam” which is among the 16 Vedic Sutras and MUX-Based Full Adders The proposed RISC processor is very simple and capable of executing 14 instructions. The achievement in this work is that savings in power in case of MAC and ALU is achieved compared to conventional ALU and MAC respectively. Also the delay is reduced in MAC and ALU in comparison with conventional ALU and MAC correspondingly. These Vedic MAC and ALU are then integrated with other blocks in processor and 64-bit Vedic processor is developed. This reduces the delay and saves area compared to conventional processor. Hence the improvement in speed of operation, and less area utilization are the key features of designed RISC processor.

Description styles of fault-tolerant finite state machines for unmanned aerial vehicles

The subject matter of this article is finite state machines (FSMs), which are used as control devices in unmanned aerial vehicles (UAVs). The goal of this study is to develop description styles for fault-tolerant FSMs in hardware description languages (HDLs) that prevent failures in the state register and in the input vector of the FSM. The tasks to be solved are as follows: development of description methods for FSM transitions from illegal states in case of failure in the state register, as well as for FSM transitions from each state in case of failure in the input vector; determination of FSM output vector values in case of the above failures; development of description styles for fault-tolerant FSMs; and investigation of the efficiency of the proposed description styles for fault-tolerant FSMs. The methods used are: the theory of finite state machines, state encoding methods of FSMs, description styles of FSMs, and Verilog hardware description language. The following results were obtained: two styles of describing fault-tolerant FSMs have been developed, safe0 and safe1, which do not increase the area and do not decrease the performance of FSMs, and in some cases allow the area to be reduced (for some examples by a factor of 4.8) and increase the performance (for some examples by a factor of 2.355). In addition, the description styles of fault-tolerant FSMs neutralize design errors when transitions are described in each state but not for all possible values of input variables. Conclusions. In this paper, the problem of designing fault-tolerant FSMs when the values of bits in the state register or in the input vector of the FSM change because of the negative external impact is described. Different ways of solving the problem at the level of FSM description in HDL are considered. Two description styles for fault-tolerant FSMs are proposed: safe0 and safe1. The fault tolerance of FSMs is provided in the following manner. When the input vector is not defined in the FSM specification for a specific state, the FSM will remain in the initial transition state, i.e. the FSM will not transit to another state. If the code of the illegal state is set in the state register, the FSM will transition to the start state. For all these faults, the safe0 style provides a zero output vector at the FSM output, whereas the safe1 style preserves the value of the previous output vector. A promising direction for future research seems to be the development of new styles and methods of FSM description, aimed at improving the FSM parameters (an area, a performance and a power consumption), as well as improving the reliability and fault tolerance of FSMs.

Teaching computer architecture by designing and simulating processors from their bits and bytes.

Teaching computer architecture (Comp-Arch) courses in undergraduate curricula is becoming more of a challenge as most students prefer software-oriented courses. In some computer science/engineering departments, Comp-Arch courses are offered without the lab component due to resource constraints and differing pedagogical priorities. This article demonstrates how students working in teams are motivated to study the Comp-Arch course and how instructors can increase student motivation and knowledge by taking advantage of hands-on practices. The teams are asked to design and implement a 16-bit MIPS-like processor with constraints as a specific instruction set, and limited data and instruction memory. Student projects include following three phases, namely, design, desktop simulator implementation, and verification using hardware description language (HDL). In the design phase, teams develop their Comp-Arch to implement specified instructions. A range of designs resulted, e.g., (a) a processor with extensive user-defined instructions resulting in longer cycle times (b) a processor with a minimal instruction set but with a faster clock cycle time. Next, teams developed a desktop simulator in any programming language to execute instructions on the architecture. Finally, students engage in Verilog Hardware Description Language (HDL) projects to simulate and verify the data-path designed during the initial phase. Student feedback and their current understanding of the project were collected through a questionnaire featuring varying Likert scale questions, some with a ten-point scale, and others with a five-point scale. Results of the survey show that the hands-on approach increases students' motivation and knowledge in the Comp-Arch course, which is centered around computer system design principles. This approach can also be effectively extended to related courses, such as Microprocessor Design, which delves into the intricacies of creating and implementing microprocessors or central processing units (CPUs) at the hardware level. Furthermore, the present study demonstrates that interactions, specifically through peer reviews and public presentations, between students in each phase increases their knowledge and perspective on designing custom processors.

Development of Circuits for Antilogarithmic Converters with Efficient Error–Area–Delay Product Using the Fractional-Bit Compensation Scheme for Digital Signal Processing Applications

Digital signal processing (DSP) has been widely adopted in sensor systems, communication systems, digital image processing, artificial intelligence, and Internet of Things applications. However, these applications require circuits for complex arithmetic computation. The logarithmic number system is a method to reduce the implementation area and transmission delay for arithmetic computation in DSP. In this study, we propose antilogarithmic converters with efficient error–area–delay products (eADPs) based on the fractional-bit compensation scheme. We propose three mathematical approximations—case 1, case 2, and case 3—to approximate the accurate antilogarithmic curve with different DSP requirements. The maximum percentage errors of conversion for case 1, case 2, and case 3 are 1.9089%, 1.7330%, and 1.2063%, respectively. Case 1, case 2, and case 3 can achieve eADP savings of 15.66%, 80.80%, and 84.61% compared with other methods reported in the literature. The proposed eADP-efficient antilogarithmic converters can achieve lower eADP and digitalized circuit implementation. The hardware implementation utilizes Verilog Hardware Description Language and the digital circuits are created via very-large-scale integration by the Taiwan Semiconductor Manufacturing Company with 0.18 µm CMOS technology. This proposed antilogarithmic converter can be efficiently applied in DSP.

Design, refinement, and enhancement of FPGA-implemented UART circuitry

This article provides an overview of the universal asynchronous receiver/transmitter, commonly referred to as Universal Asynchronous Receiver/Transmitter (UART). The UART stands as a noteworthy exemplar of a serial communication protocol, facilitating the exchange of data within a serial connection while accommodating full-duplex communication. The architecture of the UART hinges upon three principal constituents: the transmitter, the receiver, and the baud rate generator, the latter essentially a frequency divider. Each of these elements is meticulously crafted using the Verilog hardware description language, thereby ensuring distinct and efficient design. Furthermore, this discourse delves into refined iterations of these implementations. For instance, it introduces the concept of a baud rate self-adaptive function and expounds upon multibyte transmission techniques. In a concerted effort to streamline circuit design and curtail the electro circuit's footprint, a deliberate decision is made to forgo the integration of a parity check module. Consequently, the chosen data format is the widely adopted 8N1 (8 data bits, 1 stop bit and no parity bit) configuration.