An Advanced Hardware Implementation of the Trial Division Algorithm for Dividers Utilizing RISC-V ISA

Abstract

In this paper, we try to design a divider based on RISC-V instruction set architecture (ISA). Since the hardware design of the divider in the ALU is very important for the CPU to implement the arithmetic function. In view of the advantages of the trial division method in the division algorithm and the popularity of the RISC-V ISA, this paper attempts to design a trial division divider utilizing the RISC-V ISA. In this design, the principle of trial division, flow chart, state diagram, RISC-V instructions of division, whole divider module and logic will be designed in detail. To test the function and feasibility, the hardware description is carried out in the Verilog hardware description language (HDL). In this description, four division RISC-V instructions are integrated. Modelsim is used to verify and test the functionality of the divider. The test waveform is used as a result to verify the feasibility of the divider.