Verification Environment Research Articles

Pilot Study on the Responsiveness of Nurses to the Patient’s Request for complementary medicine

Introduction: When it comes to integrative medicine, the nurses are "caught in a trap" of their own views and developed competencies, as well as the views of the institution and the country where they work. The pilot study’s objective was to explore what is the expected reaction of nurses to the patient’s request for complementary treatment with tea in hospitals where integrative nursing has not yet been normatively recognised.
 Methods: The quantitative research approach with a survey was used. Nonprobability sampling covered 506 persons from Southeast Slovenia, paticipating voluntarily: nurses, nursing students, patients and other persons. Respondents were to choose among the 11 previously prepared scenarios of possible responses of the nurse.
 Results: Significant differences regarding the expected reaction of nurses both within the groups, as well as between the groups of respondents were found. The most possible critical response of nurses was to offer the tea which is daily available on the ward. A fifth of respondents believe that the patient’s tea would be provided by the visiting relatives.
 Conclusion: Due to the prepared scenarios, findings and given orientations for further research, the study can be further implemented in the international environment for empirical verification.

A power-optimized, area-efficient implementation of Connection-Then-Credit NoC physical layer

This paper discusses the implementation details of a complete NoC physical layer, basically, the Networks-on-Chip (NoC) routers, links and interfaces. A cycle-accurate RTL design details of complete NoC using a mesh-topology is presented with a special attention to the design of the NoC interface. The proposed implementation provides a complete end-to-end solution for an NoC system in a modular architecture, along with its advanced verification environment, to serve as a development and test platform for future NoC research. The paper also analyzes the performance of the Connection-Then-Credit (CTC) protocol and compares it to the conventional Credit-based (CB) protocol using standard traffic patterns, as well as its post-synthesis implementation results using TSMC 40nm low-power CMOS technology. Through the addition of a low-power controller to the CTC-based NoC interfaces, our experimental results show a significant efficiency improvement in terms of power-savings, latency and area overhead. The CTC implementation achieved 21.46% saving in power consumption for the VOPD benchmark. In terms of gate-count, the CTC implementation of VOPD, MPEG, and MWD benchmarks achieved 14.40%, 34.05%, and 7.44% less gate counts, respectively.

UVM-powered hardware/software co-verification

In traditional verification environment, hardware and software involve isolated design and verification. Due to the demise of Moore's law, the processor's frequency is no longer increasing. This demise of Moore's law and time-to-market pressures drive the wave of new technology where hardware and software are tightly integrated. This is done in order to increase the speed of computation. Moreover, in domains like Data Analytics, data has to be processed in real time and that too at low latency. Solarflare's Application On-load Engine (AOE) represents a platform where an FPGA processing engine integrates with a low latency server for applications that require real time and low latency of data processing. This is where co-verification provides a solution for integration of hardware and software. Universal Verification Methodology (UVM) doesn't support co-verification and uses Direct Programming Interface (DPI) for co-simulation. Vlang, which is built on the top of D, a systems programming language, has complete implementation of UVM version 1.2. In co-verification, emulation of software is run along with the hardware verification where, software is emulated separately on Instruction Set Simulator (ISS).

Performance verification for robot missions in uncertain environments

Establishing a-priori mission performance guarantees is crucial if autonomous robots are to be used with confidence in missions where failure could incur high costs in life and property damage. Automatic mission software verification, in addition to simulation and experimental benchmarking, is a key component of the solution for establishing performance guarantees. This component requires automatically verifying that the software constructed by the mission designer when executed in a partially known environment will adhere to the performance guarantee. In prior work we developed VIPARS, a unique approach to verifying performance guarantees for autonomous behavior-based robot software based on a combination of static analysis and Bayesian networks. While that approach produced fast and accurate verification of single robot missions with robot motion uncertainty, it did not address multiple-robot missions or any form of uncertainty related to environment geometry.This paper addresses the challenges involved in building a software tool for verifying the behavior of a multi-robot waypoint mission that includes uncertainly located obstacles and uncertain environment geometry as well as uncertainty in robot motion. An approach is presented to the problem of a-priori specification of uncertain environments for robot program verification. Two approaches to modeling probabilistic localization for verification are presented: a high-level approach and an approach that allows run-time localization code to be embedded in verification. Verification and experimental validation results are presented for several autonomous robot missions, demonstrating the accuracy of verification and the mission-specific benefit of localization

Functional verification based platform for evaluating fault tolerance properties

The fundamental topic of this article is the interconnection of simulation-based functional verification, which is standardly used for removing design errors from simulated hardware systems, with fault-tolerant mechanisms that serve for hardening electro-mechanical FPGA SRAM-based systems against faults. For this purpose, an evaluation platform that connects these two approaches was designed and tested for one particular casestudy: a robot that moves through a maze (its electronic part is the robot controller and the mechanical part is the robot itself). However, in order to make the evaluation platform generally applicable for various electro-mechanical systems, several subtopics and sub-problems need to solved. For example, the electronic controller can have several representations (hard-coded, processor based, neural-network based) and for each option, extendability of verification environment must be possible. Furthermore, in order to check complex behavior of verified systems, different verification scenarios must be prepared and this is the role of random generators or effective regression tests scenarios. Also, despite the transfer of the controller to the SRAM-based FPGA which was solved together with an injection of artificial faults, many more experiments must be done in order to create a sufficient fault-tolerant methodology that indicates how a general electronic controller can be hardened against faults by different fault-tolerant mechanisms in order to make it reliable enough in the real environment. All these additional topics are presented in this article together with some side experiments that led to their integration into the evaluation platform.

Expanding the UVM Register Model towards Automation and Simplicity of Use

The standard UVM register package contains built-in test sequences library which is used to perform most of the basic register and memory tests. These sequences are very useful at IP level verification but at SoC level verification, these sequences take very long time to run. Similarly, currently users require strong knowledge of SystemVerilog UVM language to use UVM_REG model. Some limitations in current UVM_REG package like no automatic data checking for memory accesses and limited support for memory burst operation were also seen. In this paper, we are describing how we addressed the above mentioned issues. We are accessing processor programmable registers and memories through a standard UVM_REG API. This API is aimed at writing simpler directed tests which require less or no SystemVerilog/UVM understanding. This API can be used to facilitate dumping register access for reuse from IP to SoC, or format outputs for use in ATE test vectors development etc. We also developed our own register/memory sequences to address the SoC level register and memory testing. Customized code is written to enhance the features of standard UVM_REG model. IP-XACT based tools are also developed to automatically generate all required verification environment files for using standard register model. Keywords: IP-XACT; Register Model; Register Sequences; SystemVerilog; Universal Verification Methodology (UVM); UVM_REG

Simulation environment based on the Universal Verification Methodology

Universal Verification Methodology (UVM) is a standardized approach of verifying integrated circuit designs, targeting a Coverage-Driven Verification (CDV). It combines automatic test generation, self-checking testbenches, and coverage metrics to indicate progress in the design verification. The flow of the CDV differs from the traditional directed-testing approach. With the CDV, a testbench developer, by setting the verification goals, starts with an structured plan. Those goals are targeted further by a developed testbench, which generates legal stimuli and sends them to a device under test (DUT). The progress is measured by coverage monitors added to the simulation environment. In this way, the non-exercised functionality can be identified. Moreover, the additional scoreboards indicate undesired DUT behaviour. Such verification environments were developed for three recent ASIC and FPGA projects which have successfully implemented the new work-flow: (1) the CLICpix2 65 nm CMOS hybrid pixel readout ASIC design; (2) the C3PD 180 nm HV-CMOS active sensor ASIC design; (3) the FPGA-based DAQ system of the CLICpix chip. This paper, based on the experience from the above projects, introduces briefly UVM and presents a set of tips and advices applicable at different stages of the verification process-cycle.

SHPbench – A Smart Hybrid Prototyping Based Environment for Early Testing, Verification and (user based) Validation of Advanced Driver Assistant Systems of Cars

Statistical analysis show that more than 90 percent of all car accidents result from human mistakes. Advanced Driver Assistant Systems (ADAS) are intended to support and assist the car driver, and therefore contribute significantly to the reduction of accidents. ADAS become more and more complex and demanding regarding hard- and software fulfilling the requirements applied onto assistant systems nowadays and in the future. They have to be considered as multi-functional multi-domain mechatronic systems. Smart Hybrid Prototyping (SHP) is a by now proven approach for handling ADAS’ demands during and to the development process, specifically for early integrated component and system testing, its verification and validation with the focus on the interaction with the driver can only be reasonably and economically met by utilizing the SHP technology. For those mentioned purposes the SHPbench, an integrated development and validation environment, has been recently developed. The SHPbench's architecture and specification is presented and evaluated by applying a representative use case of an ADAS development process. This paper documents the use case setup, process steps and test results.

전압계측기반 CVR제어 알고리즘 개발 및 검증을 위한 RTDS-MATLAB 연동 시뮬레이션 환경 개발

CVR은 계통의 전압을 감소시켜 소비 전력을 줄이는 기술로, 과거 많은 실증과 연구가 진행되어 왔다. 최근, SCADA 기반 또는 AMI 기반의 VVC가 개발되면서 CVR이 중요한 운영 방식이 되었다. CVR은 다양한 계측기를 사용하여 폐루프 제어(closed loop control)방식으로 최적 VVC제어 지령치를 결정한다. 본 논문에서는 전압 계측기반 CVR제어 알고리즘 개발 및 검증을 위한 RTDS-MATLAB 연동 환경을 구현하였다. RTDS를 이용하여 배전 계통의 전압제어기기들을 모델링하고 MATLAB으로 RTDS의 모의 계통의 전압을 계측하고 제어할 수 있는 제어기를 구성하였다. 무효전력 제어기기인 캐패시터는 계통의 전압을 평탄화하고 계통의 전압 기반으로 OLTC의 탭 제어를 하여 계통의 전압을 낮추는 제어 알고리즘을 MATLAB을 통해 구현하였다. 시뮬레이션을 통해 제안한 시스템을 검증하였다. CVR is a technique for reducing power consumption by reducing the voltage of the system and many demonstrations and studies have been conducted in the past. Recently, SCADA-based or AMI-based VVC have been developed and the CVR is used as an important operation mode. Using a variety of instruments, CVR determines the optimal VVC control references by closed loop control. In this paper, we implemented RTDS-MATLAB integrated simulation environment for development and verification of CVR control algorithm based on voltage measurement. The voltage control device of distribution system was modeled using RTDS and MATLAB has constructed a controller that can measure and control the voltage of the simulation system of RTDS. After the capacitor, which is a reactive power control device, flattens the voltage of the system, the control algorithm reduces the voltage of the system by tap control of the OLTC based on the flatten voltage. The proposed system was verified by simulations.

Unified and Modular Modeling and Functional Verification Framework of Real-Time Image Signal Processors

In VLSI industry, image signal processing algorithms are developed and evaluated using software models before implementation of RTL and firmware. After the finalization of the algorithm, software models are used as a golden reference model for the image signal processor (ISP) RTL and firmware development. In this paper, we are describing the unified and modular modeling framework of image signal processing algorithms used for different applications such as ISP algorithms development, reference for hardware (HW) implementation, reference for firmware (FW) implementation, and bit-true certification. The universal verification methodology- (UVM-) based functional verification framework of image signal processors using software reference models is described. Further, IP-XACT based tools for automatic generation of functional verification environment files and model map files are described. The proposed framework is developed both with host interface and with core using virtual register interface (VRI) approach. This modeling and functional verification framework is used in real-time image signal processing applications including cellphone, smart cameras, and image compression. The main motivation behind this work is to propose the best efficient, reusable, and automated framework for modeling and verification of image signal processor (ISP) designs. The proposed framework shows better results and significant improvement is observed in product verification time, verification cost, and quality of the designs.

The spirit of ghost code

In the context of deductive program verification, ghost code is a part of the program that is added for the purpose of specification. Ghost code must not interfere with regular code, in the sense that it can be erased without observable difference in the program outcome. In particular, ghost data cannot participate in regular computations and ghost code cannot mutate regular data or diverge. The idea exists in the folklore since the early notion of auxiliary variables and is implemented in many state-of-the-art program verification tools. However, ghost code deserves rigorous definition and treatment, and few formalizations exist. In this article, we describe a simple ML-style programming language with mutable state and ghost code. Non-interference is ensured by a type system with effects, which allows, notably, the same data types and functions to be used in both regular and ghost code. We define the procedure of ghost code erasure and we prove its safety using bisimulation. A similar type system, with numerous extensions which we briefly discuss, is implemented in the program verification environment Why3.

VERIFICATION OF AMBA AXI BUS PROTOCOL IMPLEMENTING INCR AND WRAP BURST USING SYSTEM VERILOG

This paper describes the development of verification environment for AMBA AXI (Advanced Extensible Interface) protocol using System Verilog. AXI supports high performance, high-frequency system designs. It is an On-Chip communication protocol. It is suitable for high-bandwidth and high frequency designs with minimal delays. It provides flexibility in the implementation of interconnect architectures and avoid use of complex bridges. It is backward-compatible with existing AHB and APB interfaces. The key features of the AXI protocol are that it consists of separate address, control and data phases. It support unaligned data transfers using byte strobes. It requires only start address to be issued in a burst-based transaction. It has separate read and write data channels that provide low-cost Direct Memory Access (DMA). This paper is aimed at the verification of various burst type transaction (INCR and WRAP) of the AXI bus protocol and the Verification Environment is built using System Verilog coding[1].

Exemplar-based Failure Triage for Regression Design Debugging

Modern regression verification often exposes myriads of failures at the pre-silicon stage. Typically, these failures need to be properly grouped into bins, which then have to be distributed to engineers for detailed analysis. The above process is coined as failure triage, and is nowadays increasing in complexity, as the size of both design logic and verification environment continues to grow. However, it remains a predominantly manual process that can prolong the debug cycle and jeopardize time-sensitive design milestones. In this paper, we propose an exemplar-based data-mining formulation of failure triage that efficiently automates both failure grouping and bin distribution. The proposed framework maps failures as data points, applies an affinity-propagation (AP) clustering algorithm, and operates in both metric and non-metric spaces, offering complete flexibility and significant user control over the process. Experimental results show that the proposed approach groups related failures together with 87 % accuracy on the average, and improves bin distribution accuracy by 21 % over existing methods.

Heterogeneous verification in the context of model driven engineering

In some cases it may be useful to represent a problem in many logical domains, since they provide different perspectives for addressing formal verification. However, the maintenance of multiple representations in separate domains can be expensive if there is neither automated assistance nor a clear formal relation between these domains. We have addressed this problem in the context of Model-Driven Engineering (MDE). We defined solid foundations of a theoretical environment for formal verification using heterogeneous verification approaches. The environment is based on the Theory of Institutions which provides a sound basis for representing MDE elements and a way for specifying translations from these elements to other domains used for verification. In this paper we present how this environment can be supported in practice within the Heterogeneous Tool Set (Hets). Hets supports heterogeneous specifications and provides capabilities for monitoring the overall correctness of a heterogeneous proof. We first extend the theoretical environment with the inclusion of an institution for the Object Constraint Language (OCL), and then we define semantic-preserving translations from the OCL-constrained MDE elements to a core language of Hets. With this we can verify basic properties of our specification, and then use the existent connections between logical domains within Hets for broadening the spectrum of domains in which complementary verification properties can be addressed.

Design and Verification of Slave Block in Ethernet Management Interface using UVM

Objective: Verification of the Slave block in Ethernet Management Interface using UVM. Methodology: Management data input output (MDIO) and Management data clock (MDC) is a two-wire interface used by Ethernet Station Management Entity to configure as well as read status from various PHY devices connected to it. Universal verification methodology is used to verify integrated designs. Verification of the Slave block in Ethernet Management Interface is done through UVM. Findings: Verification environment for the Slave Block in Ethernet Management Interface is built using UVM. 94.44% functional coverage and 97.96 code coverage is achieved. Applications: Ethernet protocol is used in the computer communication.

Stochastic costly state verification and dynamic contracts

I consider a dynamic costly state verification environment in which a risk-averse agent enters into a contract with a risk-neutral principal. The agent has random income which is unknown to the principal but can be verified at a cost. The principal can commit to executing random verifications.I extend the standard recursive methods to study the problem and show that it is optimal to set verification probabilities strictly less than 1. If the agent׳s absolute risk aversion declines sufficiently slowly, the principal will use verification regardless of its cost. If the agent's income is verified then he would get consumption and continuation utility strictly higher than if his income were not verified.

Low-Cost Simulation and Verification Environment for Micro-Satellites

Low-Cost Simulation and Verification Environment for Micro-Satellites

Implementation and Verification of Synchronous FIFO using System Verilog Verification Methodology

Developing complex nature of patterns & concurrency of Integrated Circuits has made conventional coordinated test- benches an unworkable answer for testing. Nowadays, testing as a word has been substituted with check. Confirmation specialists need to guarantee what goes to the plant for assembling is an exact representation of the specification of configuration. Verification is the maximum time consuming stage in the whole design process, thus it has become a necessity to minimize the time required to encounter the confirmation necessities. The relentless growth in the complexity of the system, has led to the requirement of a more advanced, well organized and automated approach for creating verification environments. As the designs gets complex, the probability of occurrence of bugs increases. This nеcеssitatеd the introduction of the verification phase for verifying the functionality of the IC and to detect the bugs at an early stage. In this paper, the synchronous FIFO design is verified using System Verilog Verification Environment.

Hardware-in-the-loop environment for verification of a small satellite's on-board software

Hardware-in-the-loop test beds are applied in industrial satellite development to verify on-board software and to simulate operational scenarios. Spacecraft attitude sensors are simulated by models, which eliminate the need to stimulate them for closed loop scenarios. Similarly, attitude actuators are simulated including actuation interaction with spacecraft dynamics behavior. This approach leads to an enormous reduction in a spacecraft's verification time. Small satellites developed by organizations like AMSAT or by universities are even more limited with respect to available staff and thus even more constrained. As a consequence, there is a need to implement a comparable approach for a hardware-in-the-loop simulation environment at lower cost than in industrial development. The University of Stuttgart has developed and verified a hardware-in-the-loop system test bed for a small satellite's on-board computer while maintaining compliance to industrial standards. Further cost reduction was achieved by applying an industrial system simulation kernel, additional open-source software, the voluntary participation of students, and cooperation with the industry. The system simulation environment connected to the on-board computer was verified by comparing its results with dedicated simulation tools of several disciplines. The latency of signal transfers between the on-board software and the simulator in closed loop operation was determined and analyzed with respect to compliance to control loops and simulation step sizes. All results have been proven to be satisfactory for application in university satellite development and are presented in this publication. This setup is now used in the frame of the on-board software verification for the Flying Laptop satellite.

Gateway Framework for In-Vehicle Networks Based on CAN, FlexRay, and Ethernet

This paper proposes a gateway framework for in-vehicle networks (IVNs) based on the controller area network (CAN), FlexRay, and Ethernet. The proposed gateway framework is designed to be easy to reuse and verify to reduce development costs and time. The gateway framework can be configured, and its verification environment is automatically generated by a program with a dedicated graphical user interface (GUI). The gateway framework provides state-of-the-art functionalities that include parallel reprogramming, diagnostic routing, network management (NM), dynamic routing update, multiple routing configuration, and security. The proposed gateway framework was developed, and its performance was analyzed and evaluated.