Verification Environment Research Articles

Virtualization Airborne Trusted General Computing Technology

Aircraft information service systems, such as airborne information systems, airborne integrated maintenance management systems, and cabin management systems, have greatly improved the ease of use and maintenance of civil aircraft. The current computing platforms used for accommodating these systems are unable to satisfy the multifaceted requirements of future information-based aircraft, such as energy conservation, emission reduction, high-performance computing, and information security protection, due to their high computing capacity, weight, and power consumption. Based on multi-core multi-threaded processors, a security hardware unit with microkernel virtualization technology and a virtualization airborne trusted general computing service architecture is proposed, and key technologies, including a high-performance processing and high-security hardware unit, virtualization management software unit, and virtualization security protection architecture were designed. By building a verification environment, the proposed platform was verified in terms of its application accommodation function, platform performance, and network security protection, for comparison with the existing platforms. The results showed that our method can fulfill the requirements of these technical indicators and is applicable, not only to new-generation civil aircraft, but also to unmanned aerial vehicles (UAVs) and emergency rescue aircraft with high-performance safety-critical computing needs.

FAUST: Design and implementation of a pipelined RISC-V vector floating-point unit

In this paper, we present Faust, a pipelined FPU for vector processing-capable RISC-V core developed within the European Processor Initiative (EPI) project. Faust is based on the open-source multi-format floating-point architecture FPnew that was extended and redesigned to support the RISC-V Vector extension specification (RVV) 1.0 and the most recent IEEE 754-2019 FP standard. Faust is extensively tested, mature and configurable, enabling ease of integration, as will be demonstrated in the paper. Faust can produce two binary32 operations or one binary64 operation per clock cycle. We have also developed FPU-V, an update of the SoftFloat-based reference model as a critical part of the UVM-based universal and extensible FPU verification environment. Faust was integrated and taped out as part of Vitruvius, a RISC-V Vector Processing unit of the EPAC1.0, the first EPI Accelerator Test Chip in GlobalFoundries 22FDX technology, and was shown fully operational at a target frequency of 1 GHz.

A Simulation and Verification Platform for Avionics Systems Based on Future Airborne Capability Environment Architecture

Avionics systems, which determine the performance, stability, and safety of aircraft, are a crucial part of aircraft. With the rapid development of the aviation industry, there are many serious problems in the process of the traditional simulation and verification of avionics systems, especially in the aspects of poor reusability of the hardware and software, poor real-time data interaction, and the high cost of development. In order to solve these problems, a simulation and verification platform for avionics systems based on the Future Airborne Capability Environment (FACE) architecture has been designed by using component and memory database technology. First, a general architecture is designed by referencing the FACE architecture, which allows flexible access to software and hardware resources of avionics systems. Second, the key technologies involved in the platform are described in detail, including scheduling management, communication management, and configuration management, which provide technical support for the simulation and verification of avionics systems. Finally, the simulation and verification environment of avionics systems is established, which realizes data interaction and management of various models, and improves the efficiency of the development and implementation of avionics systems.

A Script-Based Cycle-True Verification Framework to Speed-Up Hardware and Software Co-Design: Performance Evaluation on ECC Accelerator Use-Case

Digital designs complexity has exponentially increased in the last decades. Heterogeneous Systems-on-Chip integrate many different hardware components which require a reliable and scalable verification environment. The effort to set up such environments has increased as well and plays a significant role in digital design projects, taking more than 50% of the total project time. Several solutions have been developed with the goal of automating this task, integrating various steps of the Very Large Scale Integration design flow, but without addressing the exploration of the design space on both the software and hardware sides. Early in the co-design phase, designers break down the system into hardware and software parts taking into account different choices to explore the design space. This work describes the use of a framework for automating the verification of such choices, considering both hardware and software development flows. The framework automates compilation of software, cycle-true simulations and analyses on synthesised netlists. It accelerates the design space exploration exploiting the GNU Make tool, and we focus on ensuring consistency of results and providing a mechanism to obtain reproducibility of the design flow. In design teams, the last feature increases cooperation and knowledge sharing from single expert to the whole team. Using flow recipes, designers can configure various third-party tools integrated into the modular structure of the framework, and make workflow execution customisable. We demonstrate how the developed framework can be used to speed up the setup of the evaluation flow of an Elliptic-Curve-Cryptography accelerator, performing post-synthesis analyses. The framework can be easily configured taking approximately 30 min, instead of few days, to build up an environment to assess the accelerator performance and its resistance to simple power analysis side-channel attacks.

Automated formal analysis of temporal properties of Ladder programs

Programmable Logic Controllers are industrial digital computers used as automation controllers in manufacturing processes. The Ladder language is a programming language used to develop software for such controllers. In this work, we consider the description of the expected behaviour of a Ladder program under the form of a timing chart, describing a scenario of execution. Our aim is to prove that the given Ladder program conforms to the expected temporal behaviour given by such a timing chart. Our approach amounts to translating the Ladder code, together with the timing chart, into a program for the Why3 environment for deductive program verification. The verification proceeds with the generation of verification conditions: mathematical formulas to be checked valid using automated theorem provers. The ultimate goal is twofold. On the one hand, by obtaining a complete proof, one verifies the conformity of the Ladder code with respect to the timing chart with a high degree of confidence. On the other hand, in the case the proof is not fully completed, one obtains a counterexample, illustrating a possible execution scenario of the Ladder code which does not conform to the timing chart.

True-Data Testbed for 5G/B5G Intelligent Network

Future mobile communications will shift from supporting the internet of everything (IoE) to facilitating interpersonal communications beyond fifth-generation (B5G) and sixth-generation (6G) mobile communications. Intelligent communications with full integration of big data and artificial intelligence (AI) will play a key role in improving network efficiency and providing high-quality service. The AI-powered mobile communications require vast volumes of data to be collected from a real network environment for systematic testing and verification because it is a rapidly growing paradigm. As a result, we create the first true-data testbed for 5G/B5G intelligent networks (TTIN), which includes on-site experimental 5G/B5G networks, data collection and storage, and an AI engine and network optimization. True network data collecting, storage, standardisation, and analysis are possible in the TTIN, allowing for data-driven networks and system-level online verification of important B5G/6G technologies.

Evaluation on the Impact of Cache Parameter Selection in Access-Driven Cache Attacks

Cache attacks exploit the hardware vulnerabilities inherent to modern processors and pose a new threat to Internet of Things (IoT) devices. Intuitively, different cache parameter configurations directly impact the attack effectiveness, but the current research on this issue is not systematic or comprehensive enough. This paper’s primary focus is to evaluate how different cache parameter configurations affect access-driven attacks. We build a flexible and configurable simulation verification environment based on the Chipyard framework. To reduce the interference of other factors, we established a baseline for each category of parameter evaluation. We propose a novel evaluation model, called Key Score Scissors Differential (KSSD), for evaluating common private and shared cache parameters under the local and cross-core attack models, respectively; among these are private cache replacement policy, private cache capacity, cache line size, private cache associativity, shared cache capacity, and shared cache associativity. Ours is the first evaluation of the shared cache under a cross-core attack model. As a result of the evaluation, the quantitative metrics can provide a reliable indication of information leakage level under the current cache configuration, which is helpful for attackers, defenders, and evaluators. Furthermore, we provide detailed explanations and discussions of inconsistent findings by comparing our results with the existing literature.

Development of a general purpose verification environment for high-level-synthesis image processing hardware with support for dynamic partial reconfiguration

Development of a general purpose verification environment for high-level-synthesis image processing hardware with support for dynamic partial reconfiguration

Analysis and Optimizations of Power Grid Network Accuracy and Efficiency

We propose a method to power specific areas of a large-scale integrated circuit, such as the core of a system-on-chip (SoC), at a voltage higher than VDD. The voltage drops with the current flowing through the power grid, resulting in I2R losses in the on-chip power circulation. This new concept for VLSI devices is based on the commercial distribution system of long-distance power transmission companies. Our design reduces the voltage to VDD levels with an integrated DC-DC converter located near the core, like how electrical systems rely on transformers. The efficiency of a distribution matrix is the percentage of total power taken from the power source and delivered to the loads (cores). We obtained the grid from data for a commercial DC/DC converter. This paper also discusses the need for highly efficient DC/DC converters that can be integrated on chip. As state-of-the-art semiconductors become smaller and smaller, silicon process variations continue to occur and affect the performance of the chip. One of the most critical steps is worst-case voltage variations that cause inductive fluctuations. Therefore, pinpointing hotspots across the power matrix network is critical to effectively utilize the right computing environment for design verification and appropriate strategies.

Verification methodology of a multi-mode radiation-hard high-speed transceiver ASIC

The second version of Low Power Giga Bit Transceiver (lpGBTv1) addresses the functional and radiation-related issues discovered during the testing of lpGBTv0 prototype. Considerable changes to the chip configuration architecture and flow were required. The Universal Verification Methodology (UVM) based verification environment was extensively refactored to address the functional verification challenges posed by the architectural changes in the chip. Additionally, the new UVM environment was designed to support extensive verification of robustness to Single Event Effects (SEE). In this paper we present the revamped UVM verification framework of lpGBTv1 and discuss the verification process, tools, techniques and metrics used to sign-off the design before submission.

Model Checking for Real-Time Attack Detection in Water Distribution Systems

Water distribution systems represents critical infrastructures. These architectures are really critical and an irregular behaviour can be reflected in human safety. As a matter of fact, an attacker obtaining the control of such of an architecture is able to perpetrate a plethora of damages, both to the infrastructure but also to people. In this paper, we propose an approach to identify irregular behaviours focused on water distribution systems. The designed approach considers formal verification environment. The logs retrieved from water distribution systems are parsed into a formal model and, by exploiting timed temporal logic, we characterize the behaviour of a water distribution system while an attack is happening. The evaluation, referred to a water distribution system, confirmed the effectiveness of the designed approach in the identification of three different irregular behaviours.

Automatic Docking Optimization Method of Bed and Chair Based on Multi-sensor Information Fusion

<p>Automatic docking is a basic function of intelligent wheelchair bed system. In order to achieve high-precision docking between intelligent wheelchair and U-shaped bed, this paper proposes an optimization method of automatic docking between bed and chair based on multi-sensor information fusion. By installing a variety of sensors, such as depth vision camera and lidar ranging, there is usually cross sensitivity when multiple sensors work together. Based on real sensing technology，wireless sensor network technology and lidar ranging equipment l, a dynamic Bayesian multi-mode information fusion method with asynchronous constraints is proposed. Wireless sensors are used to collect wheelchair pose information in real time. By analyzing the characteristics of the observation information of various sensors, the complementary and redundant information of various sensors in space and time is combined according to optimization criteria. The data fitting between multi-sensor information is carried out efficiently and quickly by surface fitting method. Based on the extended Kalman filter algorithm, the information fusion of IMU and combined sensing unit is realized, and the analysis model is established. Finally, the feasibility of the method is verified by Matlab simulation and the use of Gazebo in ROS to build a simulation experiment environment for fusion algorithm verification.</p> <p> </p>

Research on Digital Twin Modeling and Simulation Technology for Distributed Resource Aggregation Regulation

Virtual power plants need to build awareness, transmission and application of information flow model, require multiple levels between virtual power plant, the virtual power plant each participation main body, regulation and control of virtual power plant and quantification of communication information transmission between the main constraints, this paper studies the distributed resources polymerization technology, the modeling and simulation of mechanical and electrical characteristics of virtual power plant communication network transmission characteristics of digital simulation technology, This paper proposes a simulation method of diversified resource aggregation regulation based on virtual group structure. By collecting the electrical characteristic change curve of each distributed unit, and stacking the transmission characteristics of communication network, digital simulation aggregation is carried out to obtain the digital model of cooperative operation and control characteristics of virtual power plant "information flow + energy flow". Through this model will be connected to Matlab/Simulink power system simulation environment for power regulation and operation simulation verification.

Suppression control strategy of MMC sub-module capacitor voltage in variable-frequency situation

Modular multilevel converter (MMC) topology has received widespread attention in flexible DC transmission, power quality control, and other fields because of its high modularity and malleability characteristics, and has become one of the most promising topologies. However, owing to the characteristics of the MMC itself, the fluctuation of the capacitor voltage of the MMC sub-module is inversely proportional to the MMC working frequency. One of the main technical challenges for MMC is effectively suppressing the fluctuation of the capacitor voltage of the MMC sub-module when working at low frequencies. This study first analyzes the reasons for the fluctuation of the MMC sub-module capacitor voltage at low frequency. Then, based on the results of this analysis, we propose a suppression control strategy for the capacitor voltage fluctuation of the MMC sub-module in variable-frequency working situations. Finally, an MMC module was built using the MATLAB/Simulink environment for simulation verification, and a five-level MMC physical experimental platform was built for experimental verification. The simulation and experimental results demonstrate that the proposed suppression control strategy for the MMC sub-module capacitor voltage effectively suppresses the fluctuation of the capacitor voltage under variable-frequency working situations.

DATSURYOKU: designing environment–body interaction for implicit muscle relief*

Decreased daily activities and tension frequently cause excessive muscle co-contractions implicitly, resulting in decreased performance and injury in sports. In this study, we modify the interaction between the environment and human body freely and temporarily, using environmental kinodynamic intervention. We target the load reduction during walking, which is realized by walking on a treadmill, where the acceleration/deceleration of the treadmill acts as the intervention. A forward dynamics simulation using a kinodynamic body model is used to design the intervention pattern. The designed intervention pattern is implemented in a real environment for verification, using a subject experiment with six subjects. The results demonstrate that the vertical component of the ground reaction force decreases by 2.14% and gastrocnemius and tibialis anterior activities decrease by 1.89% and % when the treadmill speed is low at heel contact and accelerates gradually. Hence, we conclude that the intervention decreases the change in the muscle length during walking, suppresses the stretch reflex, and reduces muscle activity. These results demonstrate the possibility to modify human motor control systems using non-invasive kinodynamic interventions, thereby realizing implicit muscle relief (DATSURYOKU) in sports and daily life, as well as to prevent their injuries.

Integrating Owicki\u2013Gries for C11-Style Memory Models into Isabelle/HOL

Weak memory presents a new challenge for program verification and has resulted in the development of a variety of specialised logics. For C11-style memory models, our previous work has shown that it is possible to extend Hoare logic and Owicki–Gries reasoning to verify correctness of weak memory programs. The technique introduces a set of high-level assertions over C11 states together with a set of basic Hoare-style axioms over atomic weak memory statements (e.g. reads/writes), but retains all other standard proof obligations for compound statements. This paper takes this line of work further by introducing the first deductive verification environment in Isabelle/HOL for C11-like weak memory programs. This verification environment is built on the Nipkow and Nieto’s encoding of Owicki–Gries in the Isabelle theorem prover. We exemplify our techniques over several litmus tests from the literature and two non-trivial examples: Peterson’s algorithm and a read–copy–update algorithm adapted for C11. For the examples we consider, the proof outlines can be automatically discharged using the existing Isabelle tactics developed by Nipkow and Nieto. The benefit here is that programs can be written using a familiar pseudocode syntax with assertions embedded directly into the program.

Artificial Intelligence Enhancements in the field of Functional Verification

Functional Verification is one of the main processes in the Research and Development of new System-on-Chip. As chips are becoming more and more complex, this step becomes an extensive bottleneck which can vastly delay the chip mass production. It is a mandatory step as the design needs to not contain any faults, to ensure proper functioning. If this step is bypassed, large major financial losses and customer dissatisfaction can happen later in the process. Additionally, if the verification process is prolonging for a long period of time, to achieve a higher quality product, it will also cause a financial impact. Therefore, the solution is to find ways to optimize this activity. This paper contains a review on how Artificial Intelligence can reduce this blockage, taking into consideration the time spent on implementing the verification environment and the time of attaining the aimed coverage percentage. The engineer will take a decision on which causes of time-consuming processes presented in the paper will be reduced, depending on project specifics and his or her experience. A candidate for optimizing the training of the Neural Network is the Nvidia’s Computer Unified Device Architecture (CUDA). CUDA is parallel computing platform that make use of the GPU, peculiarly of the CUDA cores located inside Nvidia GPUs.

Moderator factors of software security and performance verification

Context:Security and performance are critical software non-functional requirements. Therefore, verification activities should be included in the development process to identify related defects, avoiding failures after deployment. However, there is a lack of understanding on factors moderating the security and performance verification, which jeopardizes organizations to improve their verification activities to assure the releasing of software fulfilling these requirements. Objective:To identify moderator factors influencing security and performance verification and actions to promote them. Methods:Case study to identify security and performance moderators factors. Rapid Literature Reviews with Snowballing to strengthen moderator factors confidence. Practitioners Survey to classify the moderator factors relevance. Results:Identification of eight security and performance moderator factors regarding organizational awareness, cross-functional team, suitable requirements, support tools, verification environment, verification methodology, verification planning, and reuse practices. Rapid Reviews confirmed the moderator factors and revealed actions to promote each. A survey with 37 practitioners allowed us to classify the moderator factors and their actions regarding their relevancy. Conclusions:The moderator factors can be considered key points to software development organizations implement/improve security and performance verification activities in regular software systems. Further investigation is necessary to support the understanding of these moderator factors when building modern software systems.

Active Fault Tolerant Control of Wind Turbine Systems using Disturbance Observer-based Sliding Mode and Time Delay Estimation

In this paper, an Active Fault Tolerant Control (AFTC) based on Time Delay Estimation (TDE), sliding mode and nonlinear disturbance observer is proposed to control the pitch angle of a wind turbine system in the presence of sensor and actuator faults and uncertainties. Time Delay Estimation (TDE) is applied as a fault estimation algorithm for the detection, isolation and compensation of the actuator fault. Then, a robust control law is synthesized to nullify uncertainty and fault effects. using a combination of sliding mode disturbance observer-based and time delay control with novel adaptation laws and a nonlinear disturbance observer. In order to mitigate chattering which comes from the discontinuous control, a nonlinear disturbance observer is designed and combined with sliding mode and time delay control. Through the proposed structure, the discontinuous gain is reduced significantly which leads to chattering reduction. Stability analysis is conducted through Lyapunov Theory. Wind speed profiles are generated using TurbSim, and simulations are performed based on a nonlinear two-mass wind turbine model which is implemented in FAST environment for verification. Finally, simulation results reveal the effectiveness of the proposed controller in the presence of uncertainty and different actuator faults such as hydraulic leakage, pump wear, and high air content in the oil.

A Tutorial on Hardware-Implemented Fault Injection and Online Fault Diagnosis for High-Speed Trains.

Electrical drive systems are the core of high-speed trains, providing energy transmission from electric power to traction force. Therefore, their safety and reliability topics are always active in practice. Among the current research, fault injection (FI) and fault diagnosis (FD) are representative techniques, where FI is an important way to recur faults, and FD ensures the recurring faults can be successfully detected as soon as possible. In this paper, a tutorial on a hardware-implemented (HIL) platform that blends FI and FD techniques is given for electrical drive systems of high-speed trains. The main contributions of this work are fourfold: (1) An HIL platform is elaborated for realistic simulation of faults, which provides the test and verification environment for FD tasks. (2) Basics of both the static and dynamic FD methods are reviewed, whose purpose is to guide the engineers and researchers. (3) Multiple performance indexes are defined for comprehensively evaluating the FD approaches from the application viewpoints. (4) It is an integrated platform making the FI and FD work together. Finally, a summary of FD research based on the HIL platform is made.