Vedic Sutras Research Articles

Design and implementation in power-efficient and thermal conductivity of vedic processor for embedded applications

An embedded system that handles critical applications requires power economy, performance and thermal management, and an efficient Vedic processor with highly efficienct thermal conductivity. The proposed contemporary processor architecture has been designed to use Vedic mathematics and elaborate power and thermal optimization approaches to formulate an Arithmetic Logic Unit (ALU). This ALU is based on Vedic Sutras to enable quick computation, high precision floating point operations, and low power consumption. Since thermal management leads to energy loss in the form of heat, the embedded processor’s thermal conductivity is enhanced using novel materials and unique ways of heat dissipation. This improves performance as well as power efficiency. The proposed approach uses extensive simulation thermal analysis by EDA tools to build an optimised embedded processor that consumes 35% less power, has 40% high thermal conductivity, is 25% faster, and utilizes 15% less area when compared to conventional embedded processors. This paper helps in furthering embedded systems research by showing how old mathematical ideas can be used in a new engineering approach to solve current technology issues. The suggested novel embedded system is more efficient and thermally resistant for IOT, mobile computing, and industrial control systems.

Comparative analysis of Vedic multiplier using Vedic sutras with existing multipliers in biomedical application

In today's computer world, a lot of real-time applications require rapid processing units. Arithmetic Logic Units (ALU) and Multiply-Accumulate (MAC) are the fundamental parts of these circuits and are necessary for their effective and rapid operation. The most significant prevalent part of digital signal processing devices is multipliers. The multiplier, adder, and registers need to be changed in order to maintain accuracy and increase execution speed, which will improve the performance of the ALU and MAC. The development of greater multipliers is being given priority for application in processors because of the increasing constraints on latency. To accelerate multiplication, it is essential to develop quicker multipliers. Vedic multipliers are preferred over different current expansions due to their low power consumption, fast operation, and efficient use of space. Vedic mathematics-based algorithms are often utilized to build quick, low-power multipliers. In addition to simulation results, this section covers the four sutras of Vedic mathematics: Urdhva Tiryakbhyam, Ekadhikena Purvena, Ekanyunena Purvena, and Nikhilam. Vedic multipliers are also compared to a variety of modern multipliers, including booth, Wallace, and array multipliers. All of the sutras are evaluated according to area, speed, power, propagation delay, and mean relative error (MRE) in the current research. The results of the study will be applied in the biomedical field.

Vedic mathematics for sustainable knowledge: a systematic literature review

PurposeThis research lies in the domain of Vedic mathematics, and it explores the application of the related Vedic sutras in different branches of mathematics, science, education, and engineering across Asia and Europe.Design/methodology/approachThe study embraced a qualitative research design followed by a systematic literature review (SLR) approach which describes the significance of Vedic mathematics. The study made use of purposive sampling through which the data were collected from 102 articles by using inclusion and exclusion criteria. It includes publication years, the types of research methods, and uses of Vedic mathematics sutras in different branches of knowledge stated by the researchers. Its goal is to offer a more thorough explanation and an evaluation of how the inquiry affected the conclusions. The articles examined in this review included all the journal articles and doctoral theses from the databases of Google Scholar, Science Direct, Scopus, and Sodhganga which were published during the period 2010–2022.FindingsThe research found that the application of the sutras of Vedic mathematics has been increasing immensely in India. The researchers in this area are fond of qualitative research methods. This research has shown that sutras of Vedic mathematics especially “Urdhvatiryakbhyam” and “Nikhilam Navatascaramana Dasastah” have been frequently used in mathematics and engineering in technical higher education. The impact of other sutras has been quite useful, which augments that in many disciplines where the applications of Vedic mathematics are prevalent, it can be functional. The study concludes by reprising the result, its limitations, and the use of Vedic mathematics as a sustainable source of knowledge.Research limitations/implicationsVedic mathematics is an area where a lot of potential applications are created in science, mathematics, engineering, and education. Even with the latest technological advancements like learning analytics, artificial intelligence has its connection with this branch of learning, which is the greatest treasure of the Indian knowledge system. The research in this area is not reported in any databases or any standard format so researchers find it difficult to locate and study this broad conceptual domain.Practical implicationsIt will help the reader and other academic stakeholders to widen their view on the new and innovative techniques of Vedic mathematics. It is advised that additional studies would look at and evaluate papers published after this time so that readers may get a wider view of the concept of Vedic mathematics.Social implicationsIt will help society to know the essence of Vedic mathematics that how useful it is. Vedic mathematics helps learners to learn in a very factual and accurate manner especially while dealing with mathematical calculations. It will enhance the problem-solving skills among learners. It will be beneficial for all types of learners which will help them to become better individuals for a nation.Originality/valueThe paper enriches understanding of the potential applications of different sutras from Vedic literature in different fields of knowledge. The outcome of the research encourages educationists and policymakers to include Vedic mathematics in the curriculum to foster quantitative reasoning and problem-solving at varied levels of learning.

Squaring Circuit Using 14nmFinFET Technology with Vedic Mathematics Approach

FinFET technology is an alternative to CMOS technology as in this technology device has higher drive current, speed, and low-power consumption. FinFET has better mobility and scaling than CMOS technology. A dedicated Squaring circuit is needed by many digital signal processors (DSP) and arithmetic and logical units (ALU). So fast, power-efficient, and compact squaring circuits can be designed with Vedic sutras. Vedic mathematics has 16 sutras and 13 sub-sutras that touch almost all different chapters of mathematics. Out of these sutras, Dwandwayoga has a duplex property that is used to find a square of an N-bit number. Also, Yavadunam is a special case for finding the square of a number that is closer to the base. This work targets a comparative analysis of these two square circuits having a Vedic approach with a conventional array multiplier. The proposed designs are implemented in micro-wind 3.9 electronic design automation tool (EDA) with 14 nm deep submicron technology post-layout. The values of model parameters are used from the current Berkeley 4 short channel model (BSIM4). It is observed that the proposed square architecture design using the Dwandwayog sutra and Yavadunam sutra achieves 185%, 272.45% delay depletion and a 122.22%, and 46.52% reduction in transistor requirements compared to the conventional array multiplier, respectively.

Semi-Custom Design of Fast Multiplier Based on Vedic Sutras

Semi-Custom Design of Fast Multiplier Based on Vedic Sutras

Implementation of 64-Bit RISC Processor Using Vedic Multiplier

Abstract: In this project, 64 bit RISC processor designed with Vedic multiplier design. Reduced Instruction Set Computer (RISC) is a design which presents better performances, higher speed of operation and favors the smaller and simpler set of instructions. In addition to multiplier which is implemented using vedic mathematics we are also proposing an adder which is mux- based full adders for building higher bit adders in an area and speed efficient which is implemented in addition as well as for compression in vedic mathematic to obtain the output. A 64 bit RISC processor designed in this paper is capable of executing more number of instructions with simple design, using the Verilog Hardware Description Language (HDL) and the design is simulated in the Xilinx Vivado 2018.3. The main achievement in this work is that the multiplier unit in Arithmetic and Logic Unit (ALU) and Multiplier and Accumulator (MAC) is implemented using Vedic Sutras. The main principle used in Vedic mathematics is to reduce the typical calculation of conventional mathematics to very simple one and hence reduce the overall computational complexity. Vedic Multiplier design is based on “Urdhva Triyakbhyam” which is among the 16 Vedic Sutras and MUX-Based Full Adders The proposed RISC processor is very simple and capable of executing 14 instructions. The achievement in this work is that savings in power in case of MAC and ALU is achieved compared to conventional ALU and MAC respectively. Also the delay is reduced in MAC and ALU in comparison with conventional ALU and MAC correspondingly. These Vedic MAC and ALU are then integrated with other blocks in processor and 64-bit Vedic processor is developed. This reduces the delay and saves area compared to conventional processor. Hence the improvement in speed of operation, and less area utilization are the key features of designed RISC processor.

Implementation of Novel 2x2 Vedic Multiplier using QCA Technology

Advantages like working at high speed, scalability, and lower power consumption make QCA technology more feasible than modern CMOS technology. QCA Technology uses electrons’ Coulombic interaction and polarization to represent binary information 0 and 1. The present paper proposes a novel XOR Gate and a Half Adder design and uses them to implement a new 2x2 Vedic Multiplier on QCA technology. A 2x2 Vedic Multiplier multiplies two inputs, of two bits each, using Urdhva-Tiryakbhyam Vedic Sutra. The proposed circuit has a reduced cell count and Quantum cost compared Co-planar Vedic Multipliers to available in the literature. QCADesigner 2.0.3 is used for the simulation and verification of all three proposed circuits.

Design and VLSI Implementation of Vedic Multiplier using 45nm Technology

Abstract: This paper proposes low-power multiplier architectures based on Vedic mathematics, which is a set of ancient Indian techniques for performing arithmetic operations. The proposed architectures use the Urdhva-Tiryagbhyam sutra from Vedic mathematics, which enables the efficient multiplication of numbers with fewer partial products. The proposed architectures have been implemented and simulated using the 45-nm CMOS technology. The simulation results demonstrate that the proposed architectures achieve significant power savings compared to conventional multipliers while maintaining reasonable area and delay. Therefore, the proposed architectures are suitable for use in low-power and high-performance applications. The Vedic multiplier consists of several sub-modules, each of which performs a specific function in the multiplication process. These submodules include the partial product generator, the multiplier, and the adder. The partial product generator generates partial products based on the input numbers and the Vedic sutras. The multiplier module then combines these partial products to create the final product. Finally, the adder module adds the product to the previous state of the circuit to generate the final result.

Applicability of Vedic sutras to study the recurring decimals

Applicability of Vedic sutras to study the recurring decimals

MODIFIED HIGH SPEED AND LOW POWER 32-BIT VEDIC MULTIPLIER DESIGN AND IMPLEMENTATION

–The multiplier speed is a significant feature as the multiplier forms an important part of many systems like FIR filters, microprocessors, DSPs etc. The multiplier is slow as compared to other parts of the system hence it is the speed determining factor of the system. An improvement in speed of the multiplier leads to an improvement in speed of the overall speed. The multiplier speed not only depends on the multiplication technique used it is also depends on the type of adder employed for the addition of the partial products. The proposedhigh speed and low power 32-bit Vedic multiplier architectures based on Vedic sutra namely, Urdhva-Triyag using Carry Save Adder(CSA) has been implemented.Among various methods of multiplication, recently Vedic multipliers are being more efficient. These sutras meant for fastercalculation.Urdhva-Triyag is more efficient than other multipliers with respect to speed. The most significant aspect of the Urdhva-Triyag sutra is, the developed multiplier generates allpartial products in one step. High speed adders are used in the architecture instead of conventional Ripple carry adders thereby reducing the delay further.Finally, the results are comparedwith conventional multipliers to show the efficiency in terms of speed.The effectiveness of theproposed method is synthesized and simulated using Xilinx tool using Verilog coding Software Tools:  Xilinx ISE 14.7 Tool Key Words:Vedic Multiplier, Urdhva-Triyagbhyam sutra, Ripple Carry Adder,Carry Save Adder.

Design, Implementation & Performance of Vedic Multiplier Based on Look Ahead Carry Adder for Different Bit Lengths

Abstract: This paper proposed the layout of Vedic Multiplier based totally on Urdhva Trigbhyam approach of multiplication. It is most effective Vedic sutras for multiplication. Urdhva triyagbhyam is a vertical and crosswise approach to discover product of two numbers. Multiplication is an essential quintessential feature in arithmetic logic operation. Computational overall performance of a DSP device is limited via its multiplication overall performance and since, multiplication dominates the execution time of most DSP algorithms. Multiplication is one of the simple arithmetic operations and it requires extensively extra hardware assets and processing time than addition and subtraction. Our work is to compare different bit Vedic multiplier structure using carry look ahead adder technique. Keywords: Carry Look Ahead Adder, Urdhva Trigbhyam, DSP algorithms, Vedic Multiplier

Implementation of Vedic Sutras to Resolve Division

Mathematical science has a lots of importance in our life, this encourages logical reasoning, critical thinking, creative thinking, abstract or spatial thinking, problem solving ability etc. Everyone requires mathematics in their daily lives. Analytical and reasoning skills are important because they help us solve problems and look for solutions.If we solve any problem based on division by using Vedic Mathematics formula such as flag method, then our time is saved as well as our logical and mental development also increases. This paper includes action research on the group of 20 students who are selected from the 50 students. This study is based on the uses of the Flag Method and Urdhava-Triyagbhyam Method to solve division problems involving tables near 60, 100. Division operations are used in many problems such as square roots, cube roots, etc. Vedic Method based on Urdhava-Triyagbhyam sutra is used by these for enhancing the mental exercise and reduced the time duration during the session.

Implementation of multiplier using Vedic mathematics

Every digital circuits need processors. Every processor performs arithmetic and logical operations. There are four arithmetic operations out of which multiplication is one of the main operation. To perform multiplication, multipliers are used. Various algorithms are used to implement multipliers. Vedic algorithm is one of the algorithm and is designed using ancient Vedic sutras. In this paper design and implementation of 4-bit vedic multiplier is done and the results are compared with 4-bit array multiplier. From the result it is observed that 4-bit vedic multiplier is efficient in terms of speed. There are 16 sutras out of these URDHVA TRIYAGBHYAM sutra is used to decrease the delay of the multiplier. This is designed using Cadence tool 45 nm technology.

Pipeline Architecture for N=K*2L Bit Modular ALU: Case study between current generation computing and Vedic computing

This paper describes a design architecture that performs mathematical operations using Vedic sutra for upward compatibility in pipeline manner. In spite of increasing the area, performance and reducing power, Vedic architecture have observed to be inherently compatible with higher efficiency for pipeline architecture. However Vedic architecture leads to additional flexibility starting from 2-bit base modules to 8-bit modules (L=1,2,3) and pipeline can be compactable to any base modules for any given length. Many researchers proposed arithmetic algorithms at simulation level using vedic sutra. These algorithm have been evaluated with better performance, area and speed. The literature has been widely found to be towards individual arithmetical operators like multiplier, square and cube and so on. A consolidated computing architecture, especially N-bit ALU is yet be realized Generalized N-bit ALU, can always be realized using pipeline modular architecture. The proposition is on realizing N-bit using ‘2L’ as base modules using ‘K’ modules in pipelining. The authors have extensively verified modular architecture for 4-Bit modules for 16 bit and 32 bit pipelined operations. Individually multiplication using Urdhva Tiryakbhyam, division using Dhwajanka sutra, square using Dwandwayoga sutra. MAC unit which involves multiplication algorithms used in FFT and IFFT using sutras of Vedic mathematics and it is possible to achieve reduce version interms of speed and delay, compared to different generations of ALU. The authors are now exploring N-bit ALU architecture FPGA implementation using Vedic sutras with flexible modular pipeline architecture and mainly targeted for Digital Signal processing applications.

Pipeline Architecture for N=K*2L Bit Modular ALU: Case study between current generation computing and Vedic computing

This paper describes a design architecture that performs mathematical operations using Vedic sutra for upward compatibility in pipeline manner. In spite of increasing the area, performance and reducing power, Vedic architecture have observed to be inherently compatible with higher efficiency for pipeline architecture. However Vedic architecture leads to additional flexibility starting from 2-bit base modules to 8-bit modules (L=1,2,3) and pipeline can be compactable to any base modules for any given length. Many researchers proposed arithmetic algorithms at simulation level using vedic sutra. These algorithm have been evaluated with better performance, area and speed. The literature has been widely found to be towards individual arithmetical operators like multiplier, square and cube and so on. A consolidated computing architecture, especially N-bit ALU is yet be realized Generalized N-bit ALU, can always be realized using pipeline modular architecture. The proposition is on realizing N-bit using ‘2L’ as base modules using ‘K’ modules in pipelining. The authors have extensively verified modular architecture for 4-Bit modules for 16 bit and 32 bit pipelined operations. Individually multiplication using Urdhva Tiryakbhyam, division using Dhwajanka sutra, square using Dwandwayoga sutra. MAC unit which involves multiplication algorithms used in FFT and IFFT using sutras of Vedic mathematics and it is possible to achieve reduce version interms of speed and delay, compared to different generations of ALU. The authors are now exploring N-bit ALU architecture FPGA implementation using Vedic sutras with flexible modular pipeline architecture and mainly targeted for Digital Signal processing applications.

FPGA Implementation of 8-Bit Vedic Multiplier for DIT-FFT Application Using Urdhva Tiryagbhyam Sutra

This paper discusses FPGA Implementation of 8-Bit Vedic Multiplier and DIT-FFT Application Using Urdhva Tiryagbhyam Sutra. Initially 8-bit Vedic multiplier performance is compared with existing multiplier such as i) Wallace tree multiplier ii) Array multiplier iii) Booth multiplier. In this work Urdhva Tiryagbhyam (upright and across) Vedic sutra is used for multiplier design which provides better performance and consumes smaller time for computation. In this work, Modified Carry Save Adder (MCSA) is used to compute the sum of partially generated products. Further the multiplier is It reduces the computational delay towards the addition of unfinished products. The proposed design uses the Verilog HDL to develop the algorithm. The XILINX 14.7 software tool is used to simulate and synthesize the code. The proposed design is used for DIT FFT application.

Vedic Arithmetic Based High Speed & Less Area MAC Unit for Computing Devices

Background: The rapid improvement in technology enables design of high-speed devices, with development of modified computational elements for FPGA implementation. With complexity increasing day-to-day, there is demand for modified VLSI computational elements. Basically, for the past decade an improvement in basic VLSI Operators like Adder, multiplier is significant. The basic multiplication operator is been completely refined in the aspects of FPGA implementation. Materials and Methods: This paper presents a design of 32-bit high-speed MAC unit based on Vedic computations. Among the many sutras of Vedic mathematics, by using the urdhvatriyagbhyam sutra the products are generated in parallel. This proposed technique results in multiplication step reduction. Results: The result shows that the proposed MAC unit, the number of steps required for multiplication and addition has been reduced, it leads to the decrease in area size. In comparison with the performance of existing method to proposed MAC, the LUT's are reduced by 50 percent. Conclusion: This paper comprehensively describes the basic Multiplication operation using urdhvatriyaghyam sutra for parallel multiplication process. Based on the Vedic sutras, the performance was analyzed on a hardware platform Spartan-3E Xilinx FPGA Device for a 32-bit MAC unit. The Implementation results shoes reduction in critical delay and area when compared to conventional booth multiplier-based MAC Design. Hence this works concludes that the proposed Vedic multiplier is suitable for constructing high speed MAC units.

Square Roots in Vedic Mathematics

This paper specially concentrates on finding the square roots of perfect as well as imperfect square numbers by the Vedic sutra Vilokanam. Generally, extracting the square root of a number is considered a tedious job. There are two methods taught in our present-day classroom by conventional approach to find square roots, which are lengthy and time consuming. But, the Vedic Sutra Vilokanam helps us to find square root of such numbers with a little practice. The technique mentioned for extracting square root for imperfect square numbers does not belong solely to Vedic Mathematics written by Swami Bharati Krishna Tirthaji Maharaja. Mathematicians have been using it as a part of their general practice. However, the technique for calculating square roots and described in Vedic Mathematics is difficult. The methods discussed and organization of the content of the paper here are intended to show the Vedic Mathematics as an extremely refined and efficient mathematical system than conventional system.

Low Power Cubic Computation Unit Using Vedic Sutras

In this era of ever blooming technology, devices are developed to be more compatible and handy for the usage of people. Diminishing on-chip power has been the major concern in this nanotechnology period. Very-large-scale integration (VLSI) is the practice of developing an integrated circuit by combining several hundreds of transistors or other devices in a single chip. VLSI allows numerous functions to be added on in a single chip. Each process has inherently higher dynamic and leakage currents. Power dissipation of devices is the main concern when it applies to portable devices. Having high on-chip power degrades the devices reliability and its lifetime. There are various methods of reducing power usage by employing different algorithms, architectures, circuit logics and technology like threshold reduction. This work presents a cubic architecture designed using Vedic sutras from Vedic mathematics. It is compared with conventional architecture. Square of a binary number can be determined by using Dwanda yoga sutra of Vedic mathematics. It focuses at low power design of the architecture. This work shows that the proposed architecture has 21.53% and 46.56 % decrease in area and power respectively.

Radix-10 Fixed Point Division Hardware

Standardization of decimal floating-point formats by IEEE in IEEE 754-2008 Standards fuelled the interest on decimal floating-point architectures among the global research community. Although decimal arithmetic architecture research attracted computer scientists for the last two decades, the major thrust was observed past the year 2008. Multiple proposals have been witnessed for decimal arithmetic units, mostly adders/subtractors, and multipliers. Very few designs have been proposed in the division domain. This article proposes decimal division hardware based on sutras from Vedic Mathematics, the ancient mathematics system. We present a Reduced Magnitude Divisor Generator which converts each digit of the actual divisor into a reduced digit set [-5, 5] using a unique combination/modification of the Vedic Sutras. The divisor digit magnitude reduction also minimizes the product set of multiplication as the single-digit multiplier belongs to the reduced digit set [0, 5] barring the sign. The sign of the dividend or the divisor is not attended during division as a simple XOR operation on the two signs provides the sign of the quotient. Peer comparison has exhibited better results for our design in terms of space and time.