Array Processor Research Articles

Leveraging Generative AI for Rapid Design and Verification of a Vector Processor SoC

Leveraging Generative AI for Rapid Design and Verification of a Vector Processor SoC

Seesaw: A 4096-bit vector processor for accelerating Kyber based on RISC-V ISA extensions

The ML-KEM standard based on Kyber algorithm is one of the post-quantum cryptography (PQC) standards released by the National Institute of Standards and Technology (NIST) to withstand quantum attacks. To increase throughput and reduce the execution time that is limited by the high computational complexity of the Kyber algorithm, an RISC-V-based processor Seesaw is designed to accelerate the Kyber algorithm. The 32 specialized extension instructions are mainly designed to enhance the parallel computing ability of the processor and accelerate all the processes of the Kyber algorithm by thoroughly analyzing its characteristics. Subsequently, by carefully designing hardware such as poly vector registers and algorithm execution units on the RISC-V processor, the support of microarchitecture for extension instructions was achieved. Seesaw supports 4096-bit vector calculations through its poly vector registers and execution unit to meet high-throughput requirements and is implemented on the field-programmable gate array (FPGA). In addition, we modify the compiler simultaneously to adapt to the instruction extension and execution of Seesaw. Experimental results indicate that the processor achieves a speed-up of 432× and 18864× for hash and NTT, respectively, compared with that without extension instructions and a speed-up of 5.6× for the execution of the Kyber algorithm compared with the advanced hardware design.

Conflict Management in Vector Register Files

The instruction set architecture (ISA) of vector processors operates on vectors stored in the vector register file (VRF) which needs to handle several concurrent accesses by functional units (FUs) with multiple ports. When the vector processor is running with high utilization, access conflicts become a major source of performance degradation. With a software model of a vector processor, we take a deep dive into the runtime impact of conflicts, their characteristics, and on ways to manage them, i.e., avoidance, resolution, and mitigation. For conflict avoidance, we study the existing approaches of banking with different static bank layouts and propose a dynamic bank layout to overcome their shortcomings. Our approach assigns newly written registers a temporarily unique starting bank. For conflict resolution, we compare different arbitration algorithms and optimize round-robin arbitration for mixed-width arithmetics by prioritizing wide operands. For conflict mitigation, operand queues (OPQs) of varying depths are studied. Our inventions are likely to increase the area efficiency of vector processors. Either, because they allow to use shallower operand queues (OPQs) while keeping the same performance, or reduce the area even further by using less banks, albeit at a performance impairment of 10 % or less. The insights of the study can further be applied to other shared-memory systems.

Co-designing ab initio electronic structure methods on a RISC-V vector architecture

Ab initio electronic structure applications are among the most widely used in High-Performance Computing (HPC), and the eigenvalue problem is often their main computational bottleneck. This article presents our initial efforts in porting these codes to a RISC-V prototype platform leveraging a wide Vector Processing Unit (VPU). Our software tester is based on a mini-app extracted from the ELPA eigensolver library. The user-space emulator Vehave and a RISC-V vector architecture implemented on an FPGA were tested. Metrics from both systems and different vectorisation strategies were extracted, ranging from the simplest and most portable one (using autovectorisation and assisting this by fusing loops in the code) to the more complex one (using intrinsics). We observed a progressive reduction in the number of vectorised instructions, executed instructions and computing cycles with the different methodologies, which will lead to a substantial speed-up in the calculations. The obtained outcomes are crucial in advancing the porting of computational materials and molecular science codes to (post)-exascale architectures using RISC-V-based technologies fully developed within the EU. Our evaluation also provides valuable feedback for hardware designers, engineers and compiler developers, making this use case pivotal for co-design efforts.

Multimodal Data Mining Based on Self Attention Feature Alignment

This study explores the application of multimodal data mining in text and image vector processing, aiming to improve the depth and breadth of data analysis by integrating information from different data types. We use the FairFace dataset combined with the CLIP model encoding layer to obtain text and image vectors, and use the K-Means clustering algorithm to achieve vector dimensionality reduction. Subsequently, we introduced the bipartite graph matching algorithm to achieve maximum matching between text vectors and image vectors, and calculated the contrastive learning loss and similarity loss. The entire process covers steps such as data preparation, feature extraction, vector dimensionality reduction, matching algorithms, and loss assessment, constructing a complete text and image matching task process. Our research contributions include using K-Means clustering algorithm to achieve vector dimensionality reduction, as well as introducing bipartite graph matching algorithm and calculating two types of losses in text and image vector matching, further improving matching quality.

CSSF-BL360: Color Segmentation-Based Bolt Localization and 0~360° Full-Scale Loosening Angle Detection in Single-Frame Images

Introduction: Bolt loosening detection plays a crucial role in ensuring structural safety. Existing research using deep learning methods has the drawback of being applicable to limited scenarios and typically requires at least two frames of images for comparison in subsequent angle detection, with a limited range of detectable angles. Method: In this study, a color segmentation method was first used to separate the red square gasket placed between the bolt and the base, thereby locating the bolt area; then, the image was perspective-corrected using the four corners of the red square gasket; finally, the red mark bars on the bolt and base were separated using the same color segmentation method, and the geometric moments of the connected domains of the mark bars were processed, combined with vector processing techniques, to achieve quantified detection of bolt loosening angles within 0~360 degrees using a single frame image. In the verification experiments, 150 images were collected from different shooting angles and distances, and the bolt areas to be tested were located using the color segmentation method, all with an IOU (Intersection over Union) greater than 0.9317. Subsequent experiments set different variables, including different shooting distances, bolt loosening angles, perspective angles, lighting conditions, bolt types, and image rotation angles. Result: The results demonstrated that the method presented in this study could accurately detect bolt loosening angles in multiple scenarios. Conclusion: Hence, it is capable of measuring loosening angles within the range of 0~360 degrees using only a single frame image. result: In the verification experiments, 150 images were collected from different shooting angles and distances, and the bolt areas to be tested were located using the color segmentation method, all with an IOU(Intersection over Union) greater than 0.9317. Subsequent experiments set different variables, including different shooting distances, bolt loosening angles, perspective angles, lighting conditions, bolt types, and image rotation angles.

MED-ChatGPT CoPilot: a ChatGPT medical assistant for case mining and adjunctive therapy.

The large-scale language model, GPT-4-1106-preview, supports text of up to 128 k characters, which has enhanced the capability of processing vast quantities of text. This model can perform efficient and accurate text data mining without the need for retraining, aided by prompt engineering. The research approach includes prompt engineering and text vectorization processing. In this study, prompt engineering is applied to assist ChatGPT in text mining. Subsequently, the mined results are vectorized and incorporated into a local knowledge base. After cleansing 306 medical papers, data extraction was performed using ChatGPT. Following a validation and filtering process, 241 medical case data entries were obtained, leading to the construction of a local medical knowledge base. Additionally, drawing upon the Langchain framework and utilizing the local knowledge base in conjunction with ChatGPT, we successfully developed a fast and reliable chatbot. This chatbot is capable of providing recommended diagnostic and treatment information for various diseases. The performance of the designed ChatGPT model, which was enhanced by data from the local knowledge base, exceeded that of the original model by 7.90% on a set of medical questions. ChatGPT, assisted by prompt engineering, demonstrates effective data mining capabilities for large-scale medical texts. In the future, we plan to incorporate a richer array of medical case data, expand the scale of the knowledge base, and enhance ChatGPT's performance in the medical field.

Utilizing serverless framework for dynamic visualization and operations in geospatial applications

ABSTRACT While substantial efforts have been invested in the development of Discrete Global Grid Systems (DGGS) spatial operations and their potential applications in the geospatial domain, it has become evident that there is a demand for an efficient and scalable system to handle the visualization of large-scale DGGS data. This study demonstrated the potential of DGGS in conjunction with the serverless framework for dynamic visualization at various resolutions, which is based on data storage and effective querying using PostgreSQL integrated into Amazon Aurora Serverless. The use of Amazon Web Services (AWS) Lambda for on-the-fly generation of hexagon geometries significantly reduced the storage requirements and improved the speed of the visualization process. In addition, we implemented on-the-fly spatial operations including point binning, thresholding, aggregation, and neighborhood operations in the DGGS, highlighting the capabilities of DGGS in vector and raster processing. The proposed system has shown promising results in terms of efficiency, scalability, and adaptability, making it a viable solution for large-scale geospatial data processing and visualization. Case studies using flood risk data and terrain data further illustrate the system’s practical applicability in on-the-fly spatial operations and rapid visualization.

Co-designing ab initio electronic structure methods on a RISC-V vector architecture.

Ab initio electronic structure applications are among the most widely used in High-Performance Computing (HPC), and the eigenvalue problem is often their main computational bottleneck. This article presents our initial efforts in porting these codes to a RISC-V prototype platform leveraging a wide Vector Processing Unit (VPU). Our software tester is based on a mini-app extracted from the ELPA eigensolver library. The user-space emulator Vehave and a RISC-V vector architecture implemented on an FPGA were tested. Metrics from both systems and different vectorisation strategies were extracted, ranging from the simplest and most portable one (using autovectorisation and assisting this by fusing loops in the code) to the more complex one (using intrinsics). We observed a progressive reduction in the number of vectorised instructions, executed instructions and computing cycles with the different methodologies, which will lead to a substantial speed-up in the calculations. The obtained outcomes are crucial in advancing the porting of computational materials and molecular science codes to (post)-exascale architectures using RISC-V-based technologies fully developed within the EU. Our evaluation also provides valuable feedback for hardware designers, engineers and compiler developers, making this use case pivotal for co-design efforts.

Optimization of mechanical and safety properties by designing interface characteristics within energetic composites

The interfacial structure has an important effect on the mechanical properties and safety of the energetic material. In this work, a mesostructure model reflecting the real internal structure of PBX is established through image digital modeling and vectorization processing technology. The microscopic molecular structure model of PBX is constructed by molecular dynamics, and the interface bonding energy is calculated and transferred to the mesostructure model. Numerical simulations are used to study the influence of the interface roughness on the dynamic compression and impact ignition response of PBX, and to regulate and optimize the mechanical properties and safety of the explosive to obtain the optimal design of the surface roughness of the explosive crystal. The results show that the critical hot spot density of PBX ignition under impact loading is 0.68 mm−2. The improvement of crystal surface roughness can improve the mechanical properties of materials, but at the same time it can improve the impact ignition sensitivity and reduce the safety of materials. The optimal friction coefficient range for the crystal surface that satisfies both the mechanical properties and safety of PBX is 0.06–0.12. This work can provide a reference basis for the formulation design and production processing of energetic materials.

Parallel Implementation of K-Best Quadrature Amplitude Modulation Detection for Massive Multiple Input Multiple Output Systems

Massive MIMO (Multiple Input Multiple Output) systems impose significant processing burdens along with strict latency requirements. The combination of large-scale antenna arrays and wide bandwidth requirements for next-generation wireless systems creates an exponential increase in frontend to backend data. Balancing the processing latency and reliability is critical for baseband processing tasks such as QAM detection. While linear detection algorithms have low computational complexity, their use in Massive MIMO scenario has heavy degradation in error performance. Nonlinear detection methods such as Maximum Likelihood and Sphere Decoding have good error performance, but they suffer from high, variable, and uncontrollable computational complexity. For such cases, the K-best QAM detection algorithm can provide required control over the system performance while maintaining near-ML error performance. In this paper, hard-output, as well as soft-output K-best QAM detection, is implemented in a CPU by utilizing the multiple cores combined with vector processing. Similarly, hard-output detection in a GPU is implemented by leveraging the SIMD (Single Instruction, Multiple Data) architecture and Warp-based execution model. The processing time per bit and the energy consumption per bit are compared for CPU and GPU implementations for QAM constellation density and MIMO array size. The GPU implementation shows up to 5× processing latency per bit improvement and up to 120× energy consumption per bit improvement over the CPU implementation for typical QAM constellations such as 4, 16, and 64 QAM. GPU implementation also shows up to 125× improvement over CPU implementation in energy consumption per bit for larger MIMO configurations such as 24 × 24 and 32 × 32. Finally, the soft-output detector is combined with a LDPC (Low-Density Parity Check) decoder to obtain the FER (Frame Error Rate) performance for CPU implementation. The FER is then combined with frame processing latency to form a Goodput metric to demonstrate the latency and reliability tradeoff.

Optimization of block-scaled integer GeMMs for efficient DNN deployment on scalable in-order vector processors

A continuing rise in DNN usage in distributed and embedded use cases has demanded more efficient hardware execution in the field. Low-precision GeMMs with optimized data formats have played a key role in more memory and computationally-efficient networks. Recently trending formats are block-scaled representations stemming from tight HW-SW co-optimization, that compress network size by sharing exponents per data block. Prior work mostly focuses on deploying such block-scaled GeMM operations on domain-specific accelerators for optimum efficiency at the cost of flexibility and ease of deployment. In this work, we exploit and optimize the deployment of block-scaled GeMMs on fully-programmable in-order vector processors using ARM SVE. We define a systematic methodology for performing design space exploration to optimally match the workload specifications with processor vector-lengths, different microkernels, block sizes and shapes. We introduce efficient intrinsics-based microkernels with effective loop unrollings, and data-transfer efficient fused requantization strategies to maximize kernel performance, while also ensuring several deployment configurations. We enable generalized block-scaled kernel deployments through tunable block sizes and shapes, which helps in accommodating different accuracy-speed trade-off requirements. Utilizing 2D activation blocks instead of conventional 1D blocks, the static and dynamic BS-INT8 configurations yielded on average 3.8x and 2.9x faster speedups over FP32 models respectively, at no accuracy loss for CNN classification tasks on CIFAR10/100 datasets.

The upgrade of the CMS electromagnetic calorimeter for HL-LHC

The High Luminosity upgrade of the Large Hadron Collider (HL-LHC) at CERN aims to achieve unprecedented levels of instantaneous and integrated luminosities, approximately 5 × 1034 cm-2 s-1 and 3000 fb-1, respectively. It is anticipated that each bunch-crossing will result in an average of 140 to 200 collisions (pileup). The lead tungstate crystals and avalanche photodiodes (APDs) in the barrel region of the electromagnetic calorimeter (ECAL) of the Compact Muon Solenoid (CMS) will remain effective. However the readout and trigger electronics will undergo complete replacement to keep the current level of performance. A dual gain trans-impedance amplifier and an application-specific integrated circuit will be installed, providing two 160 MS/s analog-to-digital converter channels, gain selection, and data compression. The increase in noise within the APDs, due to radiation-induced dark current, will be alleviated by reducing the operating temperature of the ECAL. Additionally, the trigger primitive formation will be shifted away from the detector and handled by powerful and flexible field-programmable gate array processors housed on the back-end electronics cards.In this document, the complete ECAL barrel readout chain design and the current state of research and development for each individual component regarding the upgrade will be described. The outcomes of recent test beam campaigns conducted at the CERN SPS, exploiting electron beams with energies of up to 250 GeV, will also be summarized. Notably, measurements pertaining to the energy resolution performance of the latest prototypes of HL-LHC ECAL readout electronics will be presented.

Design and Implementation of Reconfigurable Array Adaptive Optoelectronic Hybrid Interconnect Shunting Network

Addressing challenges regarding Hybrid Optoelectronic Network-on-Chip systems, such as congestion control, their limited adaptability, and their inability to facilitate optoelectronic co-simulation, this study introduces an adaptive hybrid optoelectronic interconnection shunt structure tailored for reconfigurable array processors. Within this framework, an adaptive shunt routing algorithm and a low-loss non-blocking five-port optical router are developed. Furthermore, an adaptive hybrid optoelectronic interconnection simulation model and a performance statistical model, established using SystemVerilog and Verilog, complement these designs. The experimental results showcase promising enhancements: the designed routing algorithm demonstrates an average 17.5% improvement in mitigating congestion at network edge nodes; substantial reductions in the required number of cross waveguides and micro-ring resonators for optical routers lead to an average path insertion loss of only 0.522 dB. Moreover, the hybrid optoelectronic interconnection performance statistical model supports the design of routing strategies and topology structures, enabling resource usage, power consumption, insertion loss, and other performance metrics to be accurately assessed.

Asynchronous co-simulation of photovoltaic power generation system based on FPGA-CPU

In order to realize the real-time electromagnetic transient simulation of grid-connected photovoltaic power generation system with small time step, a heterogeneous multiplexed parallel real-time simulation method based on field programmable gate array (FPGA) and central processor is studied. According to the simulation accuracy requirements of the high and low frequency decoupling module, a differentiated simulation step size is used to solve the problem, and a 1us/50us FPGA-CPU multi-rate real-time simulation platform is constructed, in which the FPGA simulation part meets the real-time requirements of small-step transient simulation through the optimization of the response matching method and the EMTP algorithm, the offline simulation results are compared with Simulink, and the model before and after optimization is analyzed, the real-time electromagnetic transient simulation results are compared with Simulink, and the model before and after optimization is analyzed. By comparing the offline simulation results with Simulink and analyzing the FPGA resource consumption before and after model optimization, the accuracy and real-time performance of the co-simulation method for real-time simulation of grid-connected photovoltaic systems are verified.

Neko: A modern, portable, and scalable framework for high-fidelity computational fluid dynamics

Computational fluid dynamics (CFD), in particular applied to turbulent flows, is a research area with great engineering and fundamental physical interest. However, already at moderately high Reynolds numbers the computational cost becomes prohibitive as the range of active spatial and temporal scales is quickly widening. Specifically scale-resolving simulations, including large-eddy simulation (LES) and direct numerical simulations (DNS), thus need to rely on modern efficient numerical methods and corresponding software implementations. Recent trends and advancements, including more diverse and heterogeneous hardware in High-Performance Computing (HPC), are challenging software developers in their pursuit for good performance and numerical stability. The well-known maxim “software outlives hardware” may no longer necessarily hold true, and developers are today forced to re-factor their codebases to leverage these powerful new systems. In this paper, we present Neko, a new portable framework for high-order spectral element discretization, targeting turbulent flows in moderately complex geometries. Neko is fully available as open software. Unlike prior works, Neko adopts a modern object-oriented approach in Fortran 2008, allowing multi-tier abstractions of the solver stack and facilitating hardware backends ranging from general-purpose processors (CPUs) down to exotic vector processors and FPGAs. We show that Neko’s performance and accuracy are comparable to NekRS, and thus on-par with Nek5000’s successor on modern CPU machines. Furthermore, we develop a performance model, which we use to discuss challenges and opportunities for high-order solvers on emerging hardware.

Extension VM: Interleaved Data Layout in Vector Memory

While vector architecture is widely employed in processors for neural networks, signal processing, and high-performance computing; however, its performance is limited by inefficient column-major memory access. The column-major access limitation originates from the unsuitable mapping of multidimensional data structures to two-dimensional vector memory spaces. In addition, the traditional data layout mapping method creates an irreconcilable conflict between row- and column-major accesses. Ideally, both row- and column-major accesses can take advantage of the bank parallelism of vector memory. To this end, we propose the Interleaved Data Layout (IDL) method in vector memory, which can distribute vector elements into different banks regardless of whether they are in the row- or column-major category, so that any vector memory access can benefit from bank parallelism. Additionally, we propose an Extension Vector Memory (EVM) architecture to achieve IDL in vector memory. EVM can support two data layout methods and vector memory access modes simultaneously. The key idea is to continuously distribute the data that needs to be accessed from the main memory to different banks during the loading period. Thus, EVM can provide a larger spatial locality level through careful programming and the extension ISA support. The experimental results showed a 1.43-fold improvement of state-of-the-art vector processors by the proposed architecture, with an area cost of only 1.73%. Furthermore, the energy consumption was reduced by 50.1%.

Predecessor on the Ultra-Wide Word RAM

We consider the predecessor problem on the ultra-wide word RAM model of computation, which extends the word RAM model with ultrawords consisting of w2\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$w^2$$\\end{document} bits (TAMC, 2015). The model supports arithmetic and boolean operations on ultrawords, in addition to scattered memory operations that access or modify w (potentially non-contiguous) memory addresses simultaneously. The ultra-wide word RAM model captures (and idealizes) modern vector processor architectures. Our main result is a simple, linear space data structure that supports predecessor in constant time and updates in amortized, expected constant time. This improves the space of the previous constant time solution that uses space in the order of the size of the universe. Our result holds even in a weaker model where ultrawords consist of w1+ϵ\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$w^{1+\\epsilon }$$\\end{document} bits for any ϵ>0\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$\\epsilon > 0 $$\\end{document}. It is based on a new implementation of the classic x-fast trie data structure of Willard (Inform Process Lett 17(2):81–84, https://doi.org/10.1016/0020-0190(83)90075-3, 1983) combined with a new dictionary data structure that supports fast parallel lookups.

An improved method for extracting essay tangency features in intelligent scoring of English essays

With the continuous improvement of teaching quality in China's colleges and universities, English teaching has received more and more attention, and the automatic scoring system for English composition has begun to be gradually applied in English teaching in colleges and universities, but the system can only score compositions objectively, which is difficult to meet the actual teaching needs. Therefore, this study first proposes a topic richness based approach for analyzing composition cut points, and then proposes a combination based automatic grading method for English compositions. Based on the above, an intelligent grading improvement method based on composition tangent feature extraction is proposed to improve the efficiency of the English composition grading system and reduce the teaching burden on teachers. The traditional grading method is to grade grammar or essays by introducing Analytic Hierarchy Process, artificial neural networks, or combining machine learning theory with multi feature fusion. However, based on the characteristics of single semantic similarity and keyword alignment, the comprehensiveness of the grading is insufficient, making it difficult to analyze the correlation between essay sentences and the overall theme. The experimental results show that the topic decision-making model proposed in this study has better deep learning performance, and its scoring accuracy shows an upward trend with the increase of the sample data size of the essay, increasing from 40.05% to 91.46%. And the main content of the learned is the irrelevant information of the first sentence of a new topic and the truncation point, which can effectively distinguish whether a sentence is a topic segmentation point, and effectively identifies whether two sentences belong to the same topic; the proposed topic segmentation model has better practicality and its ability to segment topics is stronger; the combined method proposed in this study The overall performance of the model is better than the composition scoring methods based on RNN and BiLSTM models. Under the same semantic vectorization processing operation, the per values present in the composition sets are all different, and this result indicates that the writers' ability and the difficulty of writing on the topics are all different. It is hoped that this study can provide some solution ideas for the research of intelligent scoring feature extraction methods in English.

On Hardware Flexibility and Heterogeneity: A Vision for Monte Carlo Codes on Incoming RISC-V Computing Devices with AI-based Cross Section

As an open-sourced instruction set and being flexible in hardware extension, RISC-V begins its pace to enter the world of high performance computing. One of the distinguished feature of processing units adopting RISC-V is its ability to add custom circuits with special purpose accelerators. As the artificial general intelligence becomes practical, AI accelerators become an indispensable part of computing devices, where RISC-V is a great fit for the CPU to glue accelerators together. A system of chip designed by Alibaba T-head is one of the early chip in the massive production adopting RISC-V CPU, where the CPU, named Xuantie-910, has a high performance design with 128-bit RISC-V vector processing units, which are designed for accelerating AI applications. OpenMC has been adapted to run on Xuantie-910. In the Monte Carlo method for reactor physics, fetching the neutron cross sections is the hotspot that takes the majority of the computational burden. The traditional point-wise cross sections are slow because of memory latency caused by accessing many nonconsecutive memory addresses. An AI model for cross section is hence proposed. With 2.2 KB of runtime size, the smallest in the published work, the data can be fetched entirely in the L1 cache during on-the-fly cross section evaluation through single memory read. The in-house AI model also covers the entire energy range, unlike only the resonance range is supported in previous work. So, the effects from memory latency is minimized. The average relative error in AI modeled U-238 elastic cross section is 0.6% from point-wise cross section. With a modified version of OpenMC on Apple M3 Max, for a VERA pin-cell problem, compared to the point-wise cross section, the adoption of AI modeled cross section reduces the total runtime by 7%, although the runtime for calculating U-238 elastic cross section causes 40% more runtime. The adoption of AI modeled U-238 elastic cross section leads to K-effective 302 pcm higher than the case of adoption of point-wise cross sections. Advantage of AI model has been verified. With AI modeled cross section, the neutron slowing down problems with pure elastic scattering on U-238 has been studied on Xuantie-910. The average relative error in 65,536 group fluxes is about 0.9% from using point-wise cross section. However, with accelerating with the 128-bit vector processing units, the performance degrades by 35%, because of the narrow 64-bit load and store interface to the vector register files. The performance with Al modeled cross section is about 1/4 of the case with point-wise cross sections. In addition, the 1,024-bit width Ara RISC-V vector processing has been used to study the cost of AI modeled cross section evaluation. Being able to access the open-sourced hardware design in SystemVerilog, cycle accurate circuit simulation is performed. Using the vector processing units, the cost is reduced to 65% of the case using scalar instructions. The 128-bit load and store interface to vector processing units is a major contributor to the speeding up. The width of the load and store interface to vector processing units should be the main optimization factor in chip design to accelerate the AI modeled cross section evaluation.