Array Processor Research Articles

Detection of Structure Characteristics and Its Discontinuity Based Field Programmable Gate Array Processor in Cancer Cell by Wavelet Transform

Digital clinical histopathology is one of the crucial techniques for precise cancer cell diagnosing in modern medicine. The Synovial Sarcoma (SS) cancer cell patterns seem to be a spindle shaped cell (SSC) structure and it is very difficult to identify the exact oval shaped cell structure through pathologist’s eye perception. Meanwhile, there is necessitating for monitoring and securing the successful and effective image data processing in the the huge network data which is also a complex one. A field programmable Gate Array (FPGA) was regarded as a necessary one for this. In this work, based on FPGA a Cancer Cell classification is made for the regulation and execution. Hence, mathematically the SSC regularity structures and its discontinuities are measured by the holder exponent (HE) function. In this research work, HE values have been determined by Wavelet Transform Modulus Maxima (WTMM) and Wavelet Leader (WL) methods with basis function of Haar wavelet based on FPGA Processor. The quantitative parameters such as Mean of Asymptotic Discontinuity (MAD), Mean of Removable Discontinuity (MRD) and Number of Discontinuity Points (NDPs) have been considered to determine the prediction of discontinuity detection between WTMM and WL methods. With the help of receiver operating characteristics (ROC) curve, the significant difference of discontinuity detection performance between both the methods has been analyzed. From the experimental results, it is clear that the WL method is more practically feasible and it gives satisfactory performance, in terms of sensitivity and specificity percentage values, which are 80.56% and 59.46%, respectively in the blue color components of the SNR 20 dB noise image.

Pipelining Strategies and Design Considerations of Predictive Current Control Method

This paper explores the pipelining strategies for the model predictive control methods. The array and vector processing methods are examined to discover their applicability in the model predictive current method. The potential benefits of the pipelining methods are investigated, and their design methodologies are scrutinized. The model predictive control is a nonlinear control technique that predicts the system dynamics. The model predictive control (MPC) provides rapid response to the load variations and guarantees robust operation. However, the lower sampling period is the main design constraint to achieve a reliable system operation. The selection of a low sampling period demands a powerful digital controller due to the increasing computational burden. To handle the high calculation burden, a field-programmable gate array (FPGA) is a powerful solution. A proper pipelining strategy enables the use of the MPC in real-time applications. In this paper, pipelining strategies and practical design considerations of the FPGA-based predictive current method are presented. The nine switch converter (NSC) is selected as an experimental case study. The experimental results are provided to demonstrate the theoretical framework. The experimental results prove the feasibility of the array processing and vector processing methods in MPC applications.

Similarity-Aware Architecture/Compiler Co-Designed Context-Reduction Framework for Modulo-Scheduled CGRA

Modulo-scheduled coarse-grained reconfigurable array (CGRA) processors have shown their potential for exploiting loop-level parallelism at high energy efficiency. However, these CGRAs need frequent reconfiguration during their execution, which makes them suffer from large area and power overhead for context memory and context-fetching. To tackle this challenge, this paper uses an architecture/compiler co-designed method for context reduction. From an architecture perspective, we carefully partition the context into several subsections and only fetch the subsections that are different to the former context word whenever fetching the new context. We package each different subsection with an opcode and index value to formulate a context-fetching primitive (CFP) and explore the hardware design space by providing the centralized and distributed CFP-fetching CGRA to support this CFP-based context-fetching scheme. From the software side, we develop a similarity-aware tuning algorithm and integrate it into state-of-the-art modulo scheduling and memory access conflict optimization algorithms. The whole compilation flow can efficiently improve the similarities between contexts in each PE for the purpose of reducing both context-fetching latency and context footprint. Experimental results show that our HW/SW co-designed framework can improve the area efficiency and energy efficiency to at most 34% and 21% higher with only 2% performance overhead.

Customizing FFT with FMA for China Accelerator

Recently, Fast Fourier Transform (FFT) was introduced to study pattern characterization in textiles. Accelerators are a promising platform to accelerate large-scale FFT computation. However, current accelerating FFT only uses the accelerator to compute, but uses a CPU as a mere task controller. Additionally, a specified interface for FFT is built into the China accelerator (CA), which severely restricts FFT parallelization and performance. Hence, we transform four multiplications and six additions into six Fused Multiply Add (FMA) operations, then reduce total float operations by 40%, assisted by FMAs equipped with a Vector Processing Unit (VPE). Moreover, we propose an Interface Adapter (IA) to cater to a specified interface and a Fused Algorithm for Interface Adapter (FAIA) to fully use both the CA and CPU to compute large-scale FFT with coordination. Experimental results validated successful performance.

Learning-Based Detection for Malicious Android Application Using Code Vectorization

The malicious APK (Android Application Package) makers use some techniques such as code obfuscation and code encryption to avoid existing detection methods, which poses new challenges for accurate virus detection and makes it more and more difficult to detect the malicious code. A report indicates that a new malicious app for Android is created every 10 seconds. To combat this serious malware activity, a scalable malware detection approach is needed, which can effectively and efficiently identify the malware apps. Common static detection methods often rely on Hash matching and analysis of viruses, which cannot quickly detect new malicious Android applications and their variants. In this paper, a malicious Android application detection method is proposed, which is implemented by the deep network fusion model. The hybrid model only needs to use the sample training model to achieve high accuracy in the identification of the malicious applications, which is more suitable for the detection of the new malicious Android applications than the existing methods. This method extracts the static features in the core code of the Android application by decompiling APK files, then performs code vectorization processing, and uses the deep learning network for classification and discrimination. Our experiments with a data set containing 10,170 apps show that the decisions from the hybrid model can increase the malware detection rate significantly on a real device, which verifies the superiority of this method in the detection of malicious codes.

Critical Assessment of Purification and Analytical Technologies for Enveloped Viral Vector and Vaccine Processing and Their Current Limitations in Resolving Co-Expressed Extracellular Vesicles.

Viral vectors and viral vaccines are invaluable tools in prevention and treatment of diseases. Many infectious diseases are controlled using vaccines designed from subunits or whole viral structures, whereas other genetic diseases and cancers are being treated by viruses used as vehicles for delivering genetic material in gene therapy or as therapeutic agents in virotherapy protocols. Viral vectors and vaccines are produced in different platforms, from traditional embryonated chicken eggs to more advanced cell cultures. All these expression systems, like most cells and cellular tissues, are known to spontaneously release extracellular vesicles (EVs). EVs share similar sizes, biophysical characteristics and even biogenesis pathways with enveloped viruses, which are currently used as key ingredients in a number of viral vectors and licensed vaccine products. Herein, we review distinctive features and similarities between EVs and enveloped viruses as we revisit the downstream processing steps and analytical technologies currently implemented to produce and document viral vector and vaccine products. Within a context of well-established viral vector and vaccine safety profiles, this review provides insights on the likely presence of EVs in the final formulation of enveloped virus products and discusses the potential to further resolve and document these components.

Flyback Photovoltaic Micro-Inverter with a Low Cost and Simple Digital-Analog Control Scheme

The single-stage flyback Photovoltaic (PV) micro-inverter is considered as a simple and small in size topology but requires expensive digital microcontrollers such as Field-Programmable Gate Array (FPGA) or Digital Signal Processor (DSP) to increase the system efficiency, this would increase the cost of the overall system. To solve this problem, based on a single-stage flyback structure, this paper proposed a low cost and simple analog-digital control scheme. This control scheme is implemented using a low cost ATMega microcontroller built in the Arduino Uno board and some analog operational amplifiers. First, the single-stage flyback topology is analyzed theoretically and then the design consideration is obtained. Second, a 120 W prototype was developed in the laboratory to validate the proposed control. To prove the effectiveness of this control, we compared the cost price, overall system efficiency, and THD values of the proposed results with the results obtained by the literature. So, a low system component, single power stage, cheap control scheme, and decent efficiency are achieved by the proposed system. Finally, the experimental results present that the proposed system has a maximum efficiency of 91%, with good values of the total harmonic distortion (THD) compared to the results of other authors.

A Vector Processor for Mean Field Bayesian Channel Estimation

Physical layer signal processing algorithms in the wireless domain are seeing increased use of machine learning algorithms, especially Bayesian methods. This work presents the hardware architecture and implementation of a vector processor for one such application, Bayesian channel estimation (CE) (BCE). The BCE vector processor supports a generic instruction set with a supplement of specialized instructions to realize Bayesian algorithms in the signal processing context. The vector processor is designed to work as an accelerator in a system-on-chip (SoC) with an AHB/AXI bus interface or as stand-alone unit. The vector processor achieves more than <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4\times $ </tex-math></inline-formula> improvement in performance when compared with a traditional CE algorithm running on a commercial vector processor. To the best of authors knowledge, this is a first known hardware implementation of a variational Bayesian inference algorithm for a wireless communication application.

On-Board Decision Making in Space with Deep Neural Networks and RISC-V Vector Processors

The use of deep neural networks (DNNs) in terrestrial applications went from niche to widespread in a few years, thanks to relatively inexpensive hardware for both training and inference, and large datasets available. The applicability of this paradigm to space systems, where both large datasets and inexpensive hardware are not readily available, is more difficult and thus still rare. This paper analyzes the impact of DNNs on the system-level capabilities of space systems in terms of on-board decision making (OBDM) and identifies the specific criticalities of deploying DNNs on satellites. The workload of DNNs for on-board image and telemetry analysis is analyzed, and the results are used to drive the preliminary design of a RISC-V vector processor to be employed as a generic platform to enable energy-efficient OBDM for both payload and platform applications. The design of the memory subsystem is carried out in detail to allow full exploitation of the computational resources in typically resource-constrained space systems.

Space-Filling Curves for Real-Space Electronic Structure Calculations

Hamiltonian matrices for Kohn-Sham calculations implemented in real space are often large (millions by millions) but very sparse. This poses challenges and opportunities for iterative eigensolvers, which often require a large number of matrix-vector multiplications. As a consequence, an efficient parallel sparse matrix-vector multiplication algorithm is desired. Here, we investigate the benefits of using Hilbert space-filling curves (SFCs) in domain partitioning. We show that the use of Hilbert SFCs in grid-point partitioning brings better locality of the grid points, improves balance of communication, and reduces communication overhead. We also demonstrate an extension of Hilbert SFCs coupled with blockwise operations. The use of blockwise operations helps exploit the vector-processing units in contemporary computational platforms. We illustrate speedup and scalability improvements for an iterative eigensolver based on the Chebyshev-filtered subspace iteration method. Using blockwise Hilbert SFCs, we solve the Kohn-Sham problem for silicon nanocrystals up to 10 nm in diameter, which contain over 26,000 atoms. We illustrate how the density of states of silicon nanocrystals evolves to the bulk limit, where Van Hove singularities are clearly apparent.

First Experience of Accelerating a Field-Induced Chiral Transition Simulation Using the SX-Aurora TSUBASA

An analysis method based on the Ginzburg-Landau equation for the superconductivity is applied to the field-induced chiral transition simulation (FICT). However, the FICT is time consuming because it takes approximately 10 hours on a single SX-ACE vector processor. Moreover, the FICT must be repeatedly performed with parameters changed to understand the mechanism of the phenomenon. The newly emerged SX-Aurora TSUBASA, the successor of the SX-ACE processor, is expected to provide much higher performance to the programs executed on the SX-ACE as is. However, the SX-Aurora TSUBASA processor has changed its architecture of compute nodes and gives users three different execution models, which leads to users’ concerns and questions in terms of how three execution models should be selectively used. In this paper, we report the first experience of using the SX-Aurora TSUBASA processor for the FICT. Specifically, we have developed three implementations of the FICT corresponding to the three execution models suggested by the SX-Aurora TSUBASA. For acceleration of the FICT, improvement of the vectorization ratio in the program execution and the efficient transfer of data to the general purpose processor as the vector host from the vector processor as the vector engine is explored. The evaluation in this paper shows how acceleration of the FICT is achieved as well as how much effort of users is required.

Performance and Power Analysis of a Vector Computing System

The performance of recent computing systems has drastically improved due to the increase in the number of cores. However, this approach is reaching the limitation due to the power constraints of facilities. Instead, this paper focuses on a vector processing with long vector length that has a potential to realize high performance and high power efficiency. This paper discusses the potential through the optimization of two benchmarks, the Himeno and HPCG benchmarks, for the latest vector computing system SX-Aurora TSUBASA. The architecture of SX-Aurora TSUBASA owes the high efficiency to making good of its long vector length. Considering these characteristics, various levels of optimizations required for a large-scale vector computing system are examined such as vectorization, loop unrolling, use of cache, domain decomposition, process mapping, and problem size tuning. The evaluation and analysis suggest that the optimizations improve the sustained performance, power efficiency, and scalability of both benchmarks. Therefore, it is clarified that the SX-Aurora TSUBASA architecture can achieve higher power efficiency due to its high sustained memory bandwidth paired with the long vector computing.

Hardware for multi-superconducting qubit control and readout* *Project supported by the State Key Development Program for Basic Research of China (Grants Nos. 2017YFA0304300 and 2016YFA0300600), the Natural Science Foundation of Beijing, China (Grant No. Z190012), the Key-Area Research and Development Program of Guangdong Province, China (Grant No. 2020B0303030001), and the Strategic Priority Research Program of Chinese Academy of Sciences (Grant

We have developed an electronic hardware system for the control and readout of multi-superconducting qubit devices. The hardware system is based on the design ideas of good scalability, high synchronization and low latency. The system, housed inside a VPX-6U chassis, includes multiple arbitrary-waveform generator (AWG) channels, analog-digital-converter (ADC) channels as well as direct current source channels. The system can be used for the control and readout of up to twelve superconducting transmon qubits in one chassis, and control and readout of more and more qubit can be carried out by interconnecting the chassis. By using field programmable gate array (FPGA) processors, the system incorporates three features that are specifically useful for superconducting qubit research. Firstly, qubit signals can be processed using the on-board FPGA after being acquired by ADCs, significantly reducing data processing time and data amount for storage and transmission. Secondly, different output modes, such as direct output and sequential output modes, of AWG can be implemented with pre-encoded FPGA. Thirdly, with data acquisition ADCs and controlAWGs jointly controlled by the same FPGA, the feedback latency can be reduced, and in ourtest a 178.4 ns latency time is realized. This is very useful for future quantum feedback experiments. Finally, we demonstrate the functionality of the system by applying the system to the control and readout of a 10 qubit superconducting quantum processor.

AERO: A 1.28 MOP/s/LUT Reconfigurable Inference Processor for Recurrent Neural Networks in a Resource-Limited FPGA

This study presents a resource-efficient reconfigurable inference processor for recurrent neural networks (RNN), named AERO. AERO is programmable to perform inference on RNN models of various types. This was designed based on the instruction-set architecture specializing in processing primitive vector operations that compose the dataflows of RNN models. A versatile vector-processing unit (VPU) was incorporated to perform every vector operation and achieve a high resource efficiency. Aiming at a low resource usage, the multiplication in VPU is carried out on the basis of an approximation scheme. In addition, the activation functions are realized with the reduced tables. We developed a prototype inference system based on AERO using a resource-limited field-programmable gate array, under which the functionality of AERO was verified extensively for inference tasks based on several RNN models of different types. The resource efficiency of AERO was found to be as high as 1.28 MOP/s/LUT, which is 1.3-times higher than the previous state-of-the-art result.

Effects of Components Nonidealities upon The Performance of Adaptive Antenna Array Processors.(Dept.E)

Effects of Components Nonidealities upon The Performance of Adaptive Antenna Array Processors.(Dept.E)

Current and future perspectives on lentiviral vector bioprocess and bioanalytical tools

Paul Carter is the Head of Vector Processing at Quell Therapeutics Limited and has over 30 years’ experience in the pharmaceutical industry, working across cell and gene therapy, biopharmaceutical and small molecule R&amp;D. Prior to joining Quell, he was leading GSK’s Downstream Process Development Group in Cell and Gene Therapy.&#160;

Streamlining geospatial data processing for isotopic landscape modeling

AbstractStable isotopic landscape modeling has become a promising approach for answering research questions in multiple disciplines. However, its application has been hindered by the difficulty for individual researchers to collect, compile, and integrate environmental and isotopic data over large spatial and temporal scales and to develop and interpret geostatistical models. To address these challenges, we developed IsoMAP (http://isomap.org), a science gateway that enables researchers to access and integrate a number of disparate and diverse datasets, develop isoscape models over selected spatiotemporal domains using geostatistical algorithms, predict maps for the stable isotopic ratios, and associate a sample's isotope value with its most likely geographic origin. One main challenge in developing IsoMAP is to efficiently integrate large heterogeneous datasets into the modeling workflow to ensure real‐time query response and timely data update. In this paper, we described how the geospatial data processing workflow was implemented in the initial version of gateway and how it has been improved by leveraging the built‐in vector and raster data processing capabilities and the materialized view object of the PostgreSQL/PostGIS database. Our experience and lessons learned will be applicable to the development of other geospatial data workflows, a common task in the cyberinfrastructure of many science disciplines.

Implementation of four dimensional space vector modulation for five phase voltage source inverter

In this paper, a Four Dimensional Space Vector Modulation (4D-SVM) is implemented for five phase Voltage Source Inverter (VSI) to improve the performance of the inverter. The 4D-SVM control technique generates switching pulses for five phase VSI system. The reference vector for 4D-SVM is identified by tracking subcubes and prisms located in the complex 4D-cubic region. The 4D-SVM for five phase inverter includes 32 switching state vectors; all the switching states are non-redundant switching states, which are located in 32 vertices of the 4D-cube. The proposed five phase inverter with 4D-SVM reduces CMV and Total Harmonic Distortion (THD) and minimized neutral current value. The minimization of CMV leads to avoid the damage of the winding and increases the life time of the motor. So for in two level inverter, the CMV is reduced up to V dc /3 times of input voltage; In this proposed system, made an attempt to reduce the CMV level below this reported value. The simulation and hardware results are verified using matlab simulink and Field Programmable Gate Array (FPGA) processor.

Relative Speed Tabulation Method for Efficient Treatment of Resonance Scattering in GPU-Based Monte Carlo Neutron Transport Calculation

A target velocity sampling method named the Relative Speed Tabulation (RST) is proposed for the efficient treatment of resonance elastic scattering in the Monte Carlo simulation utilizing graphics processing units (GPU). The RST method samples the relative speed between a neutron and a target nucleus by employing pretabulated probabilities of relative speeds. The target velocity is then determined from the sampled relative velocity and the neutron speed. The motivation was to avoid the rejection process of the Doppler Broadening Rejection Correction (DBRC) method, which can incur a significant reduction in the parallel performance of vector processors, such as GPUs, due to its largely varying rejection rates. The RST can also overcome the weakness of large variance of the Weight Correction Method (WCM), which would involve drastic changes in neutron weights. The verification results obtained for the Mosteller benchmark problems demonstrate that the RST is equivalent to the DBRC in accuracy, while the calculation speed remains at the same level of the WCM.

OpenCL-like offloading with metaprogramming for SX-Aurora TSUBASA

This paper presents an OpenCL-like offload programming framework for NEC SX-Aurora TSUBASA (SX-Aurora) and also discusses the benefit of employing metaprogramming to describe architecture-specific parts of the programs. Unlike traditional vector systems, one node of an SX-Aurora system consists of a host processor and some vector processors on PCI-Express cards, which are called a vector host and vector engines, respectively. Since the standard OpenCL execution model does not naturally fit in the vector engine, this paper discusses how to adapt the OpenCL specification to SX-Aurora while considering the trade off between performance and code portability. This paper employs OpenCL to minimize non-portable parts of an application code for offload programming, and then metaprogramming to describe the non-portable parts. Performance evaluation results clearly demonstrate that, with a moderate programming effort, the proposed framework can express the collaboration between a vector host and a vector engine so as to make a good use of both of the two different processors. By delegating the right task to the right processor, an OpenCL-like program can fully exploit the performance of SX-Aurora. Moreover, metaprogramming can express vectorization-aware performance optimization to enhance the performance portability across different architectures including SX-Aurora.