Output Frequency Of VCO Research Articles

Equivalent-circuit modeling of a MEMS phase detector for phase-locked loop applications

This paper presents an equivalent-circuit model of a MEMS phase detector and deals with its application in phase-locked loops (PLLs). Due to the dc voltage output of the MEMS phase detector, the low-pass filter which is essential in a conventional PLL can be omitted. Thus, the layout area can be miniaturized and the consumed power can be saved. The signal transmission inside the phase detector is realized in circuit model by waveguide modules while the electric-thermal-electric conversion is illustrated in circuit term based on analogies between thermal and electrical variables. Losses are taken into consideration in the modeling. Measurement verifications for the phase detector model are conducted at different input powers 11, 14 and 17dBm at 10GHz. The maximum discrepancies between the simulated and measured results are 0.14, 0.42 and 1.13mV, respectively. A new structure of PLL is constructed by connecting the presented model directly to a VCO module in the simulation platform. It allows to model the transient behaviors of the PLL at both locked and out of lock conditions. The VCO output frequency is revealed to be synchronized with the reference frequency within the hold range. All the modeling and simulation are performed in Advanced Design System (ADS) software.

A 4.2 mm$^{2}$ 72 mW Multistandard Direct-Conversion DTV Tuner in 65 nm CMOS

This paper presents a direct-conversion DTV tuner for both VHF and UHF bands. The proposed tuner achieves a noise figure of 2.5-3.5 dB at VHF band and 2-3 dB at UHF band while the LNA consumes only 3.5 mW. An external band-pass LC filter is adopted for RF pre-filtering and providing DC conduction path for noise cancelling balun LNA. The system-level co-design of the LNA and pre-selecting filter further help to obtain 33 dB third-order harmonic rejection ratio without using harmonic rejection mixers. A quantization-noise-compensated fractional- N frequency synthesizer is implemented, achieving 0.5 ° integrated phase error (1 kHz to 4 MHz) at 666 MHz, and suppressing out-of-band ΣΔ noise by 20 dB. The proposed PLL injects compensation current into the loop filter during the PFD delay time, which precisely tracks the VCO output frequency. Highly reconfigurable analog baseband with 0.5-4 MHz bandwidth and 6-54 dB gain is integrated. The tuner is implemented in 65 nm CMOS process, occupies an area of 4.2 mm2, and consumes only 72 mW from a 1.2 V voltage supply.

A 30GHz Wideband CMOS Injection-Locked Frequency Divider for 60GHz Transceiver

In this paper, a 30 GHz wide locking-range (26.2 GHz-35.7 GHz) direct injection-locked frequency divider (ILFD), which operating in the millimeter-wave (MMW) band, is presented. The locking range of the ILFD is extended by using differential injection topology. Besides, varactors are used in RLC resonant tank for extending the frequency tuning range. The post simulation results show that a wide locking-range of 9.5 GHz (30.7%) is achieved. When the VCO output frequency varies from 26.85 GHz to 34.42 GHz, the proposed ILFD can achieve divide-by-two correctly. Designed in 0.13 μm CMOS technology, the ILFD occupies a core area of 0.76 mm2 while drawing 7 mA of current from 2.5 V power supply.

Phase-Locked Loop with Leakage and Power/Ground Noise Compensation in 32nm Technology

This paper presents two novel compensation circuits for leakage current and power supply noise (PSN) in phase locked loop (PLL) using a nanometer CMOS technology. The leakage compensation circuit reduces the leakage current of the charge pump circuit and the PSN compensation circuit decreases the effect of power supply variation on the output frequency of VCO. The PLL design is based on a 32nm predictive CMOS technology and uses a 0.9 V power supply voltage. The simulation results show that the proposed PLL achieves 88% jitter reduction at 440 MHz output frequency compared to the PLL without leakage compensator and its output frequency drift is little to 20% power supply voltage variations. The PLL has an output frequency range of 40 M~725 MHz with a multipli-cation range of 1-1023, and the RMS and peak-to-peak jitter are 5psec and 42.7 psec, respectively.

A 32nm and 0.9V CMOS Phase-Locked Loop with Leakage Current and Power Supply Noise Compensation

This paper presents two novel compensation circuits for leakage current and power supply noise (PSN) in phase locked loop (PLL) using a nanometer CMOS technology. The leakage compensation circuit reduces the leakage current of the charge pump circuit which becomes more serious problem due to the thin gate oxide and small threshold voltage in nanometer CMOS technology and the PSN compensation circuit decreases the effect of power supply variation on the output frequency of VCO. The PLL design is based on a 32㎚ predictive CMOS technology and uses a 0.9V power supply voltage. The simulation results show that the proposed PLL achieves a 88% jitter reduction at 440㎒ output frequency compared to the PLL without leakage compensator and its output frequency drift is little to 20% power supply voltage variations. The PLL has an output frequency range of 40M~725㎒ with a multiplication range of 1-1023, and the RMS and peak-to-peak jitter are 5ps and 42.7ps, respectively.

Improved capacitance measurement by means of resonance locking

We describe a new LC method of capacitance measurement. The method consists of a synthesis of LC resonance and LC oscillator methods. The LC tank circuit is driven by a voltage-controlled oscillator (vco) and is included in an analogue phase-locked loop; the loop is designed to lock with no phase difference between current flow and driving voltage in the tank circuit. The system effectively tracks the resonance peak as the capacitance changes, thus allowing automatic measurement of capacitance by monitoring the vco input voltage or output frequency. The measurement bandwidth is dependent only on phase detector response, and can extend to the range of several MHz. The accuracy of this 'resonance locked loop' is equivalent to that of conventional systems and the dynamic range is considerably improved; a system with measured accuracy of 11 aF and bandwidth of 100 kHz has been constructed, and has been used to measure high-frequency submicrometre movements of piezoelectric actuators.