Defect Density Variation Research Articles

Point defect yield model for wafer scale integration

Yield projections are a primary consideration in wafer scale integration. The author develops a point defect yield model for a two-way redundancy scheme appropriate for random logic. The model assumes that the fault-causing defects are randomly distributed locally but that the defect density can vary across a wafer as well as from one wafer to another. Examples are given to illustrate the strong dependence of the results on clustering of defects and on the redundancy partitioning. The importance of the distinction between on-wafer and wafer-to-wafer variations in defect density is demonstrated. Complications associated with the occurrence of small numbers of highly correlated defects are discussed.

The effects of wafer to wafer defect density variations on integrated circuit defect and fault distributions

A method for modeling the variations in defect levels in circuits produced on modern integrated circuit manufacturing lines is described in this paper. The effects on defect and fault distributions are derived. A deficiency in some previous yield models is eliminated.

MOS Gate Oxide Defects Related to Treatment of Silicon Nitride Coated Wafers Prior to Local Oxidation

This report details an investigation into the variation of gate oxide defect densities resulting from different treatments of NMOS processed Si wafers immediately after deposition of the LPCVD Si nitride layer used as a local oxidation mask. Data are provided that show that high pressure water scrubbing aggravates a flaw or dislodges an inclusion in the as‐deposited layer. Localized (∼1 μm diam), thin gate oxide defects subsequently form at these sites, allowing premature dielectric breakdown.

Positron lifetime studies on thorium oxide powders

Abstract Positron lifetime spectra have been studied for ThO2. powders, calcined at different temperatures and having different particle sizes. Three lifetime components could be resolved, the longest component being of low intensity. An observed strong dependence on the particle size of the annihilation process and the variation of positronium diffusion constant is explained on the basis of defect density variations in these powders.

Study of positron lifetime spectra in UO 2 powders

Positron lifetime spectra were measured in UO 2 powders having different particle sizes. The annihilation process was found to have a strong particle size dependence. Results have been interpreted on the basis of defect density variations in these powders.

A hard disc system; an Ising-like behaviour in a thin layer

The properties of hard discs in a channel (separation D) have been studied for the σ ⪕ D ⪕ 2σ regime (σ = diameter of the discs), since this regime connects the one-dimensional and two-dimensional cases which exhibit very different free energy functions. Both mechanical and computer simulation results clearly show qualitatively different states of order at low and high packing densities, respectively. A theoretical analysis of the system is presented utilizing a ‘double line’ model. The predicted variation of defect density versus packing density agrees phenomenologically with the results of the mechanical and computer simulations.

The Dependence of the SiO2 Defect Density on Both the Applied Electric Field and the Oxide Thickness

By using liquid crystals in contact with the oxide and simultaneously applying an electric field across such a sandwich structure, defective regions can be nondestructively identified. By examining the number of defects as a function of the applied electric field and oxide thickness, it is possible to obtain information on the variation of the defect density with the applied electric field and oxide thickness. Experiments of this type indicate that the defect density was found to exponentially increase with the square root of the positive applied electric field. Also the total leakage current density was found to exponentially increase with the square root of the positive applied electric field in the presence of the liquid crystals. The defect diameter was found to be in the range of 0.14–0.42 μm. For oxide thickness above 0.2 μm the defect density exponentially decreases with increasing oxide thickness. But for oxide thicknesses less than 0.2 μm it is very difficult to judge the variation since the defect density increases very rapidly with decreasing oxide thickness. Spikes of were observed to protrude into the silicon substrate for thin oxides (about 0.1 μm); however, these spikes could be eliminated by increasing the oxide thickness (greater than 0.3 μm). With increasing oxide thickness the interface becomes evener and the density of the interface irregularities decreases. The electron space‐charge effects were postulated as a second explanation for the variation of the oxide defect density with the oxide thickness. This theoretical treatment agrees well with the experimental results. The space‐charge (electron) density in the oxide was equal to which is in agreement with the trap density of the silicon dioxide.

Thickness and field dependence of defects in silicon dioxide

The Liquid Crystal Technique is used to determine the variation of saturation defect density with applied field and film thickness, in thermal oxides of silicon. The results are consistent with trap controlled space charge limited currents occurring in the region of a defect. Various parameters of the free charge, and traps, are estimated.

Defect density variation with deposition rate in snsb thin films from annealing study of electrical resistance

SnSb thin films of the same thickness (600 Å) vacuum deposited at room temperature on glass substrates at various deposition rates were heated to a maximum temperature of about 300°C and the changes in the electrical resistance with temperature were recorded. From the resistance vs temperature data “initial lattice distortion energy spectra” i.e. the variation of the defect density with its activation energy, of the films is obtained. It is found that the area of the spectra decreases with an increase in the deposition rate thereby indicating that the defect density of the film decreases with increasing deposition rate. The observed decrease in the defect density of the films with increasing deposition rate has been satisfactorily explained with the help of nucleation and growth phenomena.

Defect density variation with depostion rate in SnSb thin films from annealing study of electrical resistance

Defect density variation with depostion rate in SnSb thin films from annealing study of electrical resistance

Heteroepitaxial InAs Grown on GaAs from Triethylindium and Arsine: II . Electrical Properties

Heteroepitaxial films of on substrates, grown by the decomposition of triethylindium and arsine, have been characterized. Films with mobilities of up to 10,000 cm2/V‐sec have been obtained. The mobility remains approximately constant with decreasing thickness up to an epitaxial layer thickness of 1 µm. A theory is presented for the variation in defect density in epitaxial layers as a function of the growth temperature and layer thickness. The carrier concentration of the layers decreases exponentially with increasing substrate temperature and decreases inversely with increasing layer thickness, in accordance with this theory.

Defect analysis and yield degradation of integrated circuits

Various attempts have been made to analyze the yield of integrated circuits in the presence of point defects. This paper analyzes the yield considering both radial and angular variation in the defect density. The effect of statistical variations in the average defect density from slice to slice is also included. Different types of defects which affect the yield are reviewed. The degradation in yield due to point defects, line defects, area defects, and defect clusters is considered in detail. A method of optimum chip placement is described, and the results of computer calculations showing yield as a function of chip size are given assuming different defect density distributions. The results are primarily applicable to large integrated circuit chips.

Equations for thermoluminescence and thermally stimulated current as derived from simple models

Equations for thermoluminescence and thermally stimulated currents are derived for simple models where transitions are strictly localized, where transitions are via a band; and where transitions are by overlap transfer. Analytical expressions for I(T) and σ(T) follow from assumptions about the relative densities of trapping states, filled trapping states, and empty recombination states; and from assumptions about the relative values of the different transition probabilities. The characteristics of glow curves are discussed in terms of relative values of the density and transition probability parameters. The models treated can be distinguished by variation of defect densities. It is shown that it is frequently possible to use experimental conditions for which the glow will have an analytical form, when the models discussed here are appropriate.

Cost-size optima of monolithic integrated circuits

A generalized cost-size relationship is derived for a monolithic circuit consisting of N identical components, taking into account variations in component density, yield, and assembly costs with N. It is intended to reveal cost trends rather than give accurate results for specific cases and deals only with fabrication costs. A yield-area relationship is used which takes into account chip-to-chip variations in defect density. It is found that the ratio (circuit cost per component/cost of discrete transistor) is a minimum at a chip size which is determined primarily by the spot defect density on the device. This optimum chip size lies between approximately 20 and approximately 60 mils square for a wide range of parameter values. State-of-the-art parameter values indicate a potential order of magnitude cost saving in integrated circuits compared with discrete transistors. The minimum value for the cost ratio is in general inversely proportional to the maximum packing density of components on a semiconductor slice and has a limiting value approximately 1/8N, N <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</inf> being the number of components which can be packed on the chip size normally used for transistors. Arrays of identical logic gates fit the circuit model used quite closely, and the curves indicate that the cost per gate in reasonably densely packed arrays can be less than the cost of a discrete transistor. The results also indicate that when systems requirements make it desirable to include larger numbers of components in one package than the optimum for one monolith, wired-chip schemes are preferable to single monoliths, the optimum chip size being smaller than that for a simple monolith.