Variable Gain Amplifier Research Articles

Integrated ExG, Vibration and Temperature Measurement Front-End for Wearable Sensing

This paper presents a programmable CMOS integrated front-end ASIC targeting the acquisition of signals in biomedical applications, including rehabilitation and treadmill exercise monitoring. The analog front-end is combined with a commercial microcontroller for clock generation, signal processing, and feedback generation. The ASIC provides a unique combination of sensing interfaces, including a dc-coupled ExG monitor including variable gain amplification with 34–60 dB tunable gain range, 31-step offset compensation, as well as a capacitive sensor readout for piezoelectric vibration measurement (which can alternatively be used as a buffer for sensors with voltage output) providing 28.6-dB attenuation and $16~V_{\mathrm {pp}}$ effective input range below 100 Hz, a 1 °C-precision thermometer, a 50-/60-Hz switched-capacitor notch filter for mains interference reduction, and an 8-bit analog-to-digital pulse-width-modulating converter. The design is realized in 180-nm technology where it occupies an area of 0.06 mm2. Measured results are reported which confirm the intended operation.

A 71–76 GHz wideband receiver front-end for phased array applications in 0.13 μm SiGe BiCMOS technology

This paper presents the design of a millimeter-wave wideband receiver front-end in a 0.13 \(\upmu\)m SiGe BiCMOS technology for phased array applications. The receiver front-end is suitable for a phased array time-division duplexing communication system where both the transmitter and the receiver share the same antenna. The monolithic microwave integrated circuit front-end comprises of quarter-wave shunt switches, a low-noise amplifier (LNA), an active phase shifter and a buffer amplifier. The quarter-wave shunt switch is designed using reverse-saturated SiGe HBTs. The transformer-based LNA utilizes a common-emitter amplifier at the first stage and a cascode amplifier at the second stage to exploit the advantages of both common-emitter and cascode topologies. The designed switch is incorporated in the input matching network of the LNA. The active phase shifter consists of variable gain amplifiers driven by a polyphase filter-based quadrature generator. The receiver front-end achieves a measured gain of 18.5 dB and a noise figure of 9 dB with a 3 dB bandwidth of 23 GHz from 56 to 79 GHz. The receiver phase can be tuned continuously from 0\(^{\circ }\) to 360\(^{\circ }\). An output referred 1-dB compression point of \(-\) 7.4 dBm is achieved at 70 GHz. The receiver consumes 116 mW of DC power and occupies a core area of \(1800\,\upmu {\text {m}} \times 475\,\upmu {\text {m}}\).

<inline-formula> <tex-math notation="LaTeX">$W$ </tex-math> </inline-formula>-Band (92–100 GHz) Phased-Array Receive Channel With Quadrature-Hybrid-Based Vector Modulator

This paper presents a $W$ -band (92–100 GHz) phased array receive channel adopting a power domain vector modulator (VM), which utilizes a 90° hybrid-coupler-based phase interpolator. The quadrature hybrid leverages its inherent functions of quadrature phase splitting and power combining to interpolate phases by combining the weighted signals from variable gain amplifiers in the power domain. Compared with prior active VMs, in the proposed VM, the phases are synthesized in a pure passive network with a matched impedance, less vulnerable to circuit nonlinearity. The distributed 90°-hybrid coupler offers a wideband operation of quadrature phasing and phase interpolation, resulting in a low phase error over the $W$ -band. The measured VM peak-to-peak gain variation for all 5-bit phase states is 7.7–11 dB at the expense of 31-mW dc power from 2.2-V supply voltage. The measured rms gain error is $P_{-1\,{\mathrm{ dB}}}$ is −4 dBm at 94 GHz at the highest gain state. In the receive channel employing the 90°-hybrid-based VM, the peak-to-peak gain variation is 23–26 dB with 9.3–11-dB NF at the expense of 50-mW dc power from 2.2-V supply voltage. The measured input $P_{-1\,{\mathrm{ dB}}}$ is −26 dBm. The chip size of the receive channel, implemented in 0.13- $\mu \text{m}$ SiGe BiCMOS process, is $1.65\times0.55$ mm $^{\vphantom {R^{l}}2}$ .

Design of a constant-bandwidth variable-gain amplifier for LTE receivers

In this study, a constant-bandwidth variable-gain amplifier (VGA) is presented for long-term evolution (LTE) receivers. The presented VGA’s description is given with a newly proposed exponential-current generator, and also the common-mode feedback and the DC-offset cancellation (DCOC) circuits. The proposed exponential current generator is based on the Taylor series approximation in such a way that it can be expanded to meet the required gain control range. The simulations are performed using the TSMC 180 nm process technology with Cadence Analog Virtuoso. The VGA has a 45 dB gain control range, 180 MHz bandwidth, 15.7 dB m the third-order input-intercept point for minimum gain and below 20 dB noise figure for maximum gain which makes it convenient for LTE receivers. The simulations also show that the bandwidth of the VGA is fairly constant over the control range. Monte Carlo simulations reveal that by using a DCOC circuit, the VGA provides 30 dB output offset rejection. The overall power consumption of the circuit is 9.1 mW under a 1.8 V power supply.

A new current mode CMOS variable gain amplifier using a new pseudo-exponential function

In this paper, a new pseudo-exponential function is described and a new CMOS exponential-control variable gain amplifier (VGA) based on the new function is introduced. No multiplier is needed in the proposed approach. The VGA operates in current mode and includes two different stages. The first stage is a simple current amplifier while the second stage is an attenuator. The overall behavior of the stages gives the new pseudo-exponential function. The VGA circuit has been designed and simulated for a 0.18 μ CMOS process. Post layout results show that the circuit has a bandwidth of 164 MHz and a gain range of 32.5 dB between − 21 and + 11.5 dB.

An Analog Front End ASIC for Cardiac Electrical Impedance Tomography.

In this paper, an end-to-end CMOS application specific integrated circuit (ASIC) for readout channel in a cardiac electrical impedance tomography system is presented. The ASIC consists of an integrated current driver for current injection, an instrumentation amplifier, variable gain amplifier at the analog front end for voltage readout from electrodes, and an on-chip 10-bit successive approximation register analog to digital converter with serial peripheral interface. The ASIC is fabricated in the CMOS 0.18 $\mu$ m process with a supply voltage of 3.3 V. Amplitude and phase extraction of the voltages is performed in the digital domain with a matched filter. A fully integrated solution for use in multiple electrode system is demonstrated. The readout chain in the ASIC achieves a minimum signal-to-noise ratio of 71dB over the frequency range of 500 Hz-700 kHz, while maintaining an average accuracy of 99.7 $\%$. Frame rates of 21 frames per second for a 32 electrode system is feasible, and the ASIC has an overall power consumption of 11.8 mW.

A Low-Cost Scalable 32-Element 28-GHz Phased Array Transceiver for 5G Communication Links Based on a <inline-formula> <tex-math notation="LaTeX">$2\times 2$ </tex-math> </inline-formula> Beamformer Flip-Chip Unit Cell

This paper presents a scalable 28-GHz phased-array architecture suitable for fifth-generation (5G) communication links based on four-channel ( $2\times 2$ ) transmit/receive (TRX) quad-core chips in SiGe BiCMOS with flip-chip packaging. Each channel of the quad-core beamformer chip has 4.6-dB noise figure (NF) in the receive (RX) mode and 10.5-dBm output 1-dB compression point (OP1dB) in the transmit (TX) mode with 6-bit phase control and 14-dB gain control. The phase change with gain control is only ±3°, allowing orthogonality between the variable gain amplifier and the phase shifter. The chip has high RX linearity (IP1dB = −22 dBm/channel) and consumes 130 mW in the RX mode and 200 mW in the TX mode at P1dB per channel. Advantages of the scalable all-RF beamforming architecture and circuit design techniques are discussed in detail. 4- and 32-element phased-arrays are demonstrated with detailed data link measurements using a single or eight of the four-channel TRX core chips on a low-cost printed circuit board with microstrip antennas. The 32-element array achieves an effective isotropic radiated power (EIRP) of 43 dBm at P1dB, a 45-dBm saturated EIRP, and a record-level system NF of 5.2 dB when the beamformer loss and transceiver NF are taken into account and can scan to ±50° in azimuth and ±25° in elevation with < −12-dB sidelobes and without any phase or amplitude calibration. A wireless link is demonstrated using two 32-element phased-arrays with a state-of-the-art data rate of 1.0–1.6 Gb/s in a single beam using 16-QAM waveforms over all scan angles at a link distance of 300 m.

Electromagnetic Energy Harvester Interface Design for Wearable Applications

This brief presents an interface design for electromagnetic energy harvesting for wearable applications. A transducer design is proposed. Multiple segments of coils with alternating winding directions improve the induced voltage and power. Due to the source’s wideband nature in target applications, we avoid the use of springs common in conventional designs. The corresponding equivalent circuit model is presented. A system-level analysis is then performed that leads to the following power interface circuit design. It includes a differential rectifier and a switched-inductor boost converter. The harvested power is maximized with a constant-resistance load that can be adjusted through a variable-gain amplifier’s gain. Implemented in a ${0.18{-}\mu }\text{m}$ CMOS process and tested at 20 Hz, measurement results show >80% impedance matching efficiency with >0.7-V input voltages. The system is able to harvest ${\sim }320~{\mu }\text{W}$ when shaken by hand at 2.5~3 Hz.

A CMOS Low-Power Digital Variable Gain Amplifier Design for a Cognitive Radio Receiver “Application for IEEE 802.22 Standard”

This paper presents the design of a new Digital Variable Gain Amplifier cell (DVGA). The proposed circuit based on transconductance, gm, amplifier and a transconductance amplifier is analyzed and designed for a cognitive radio receiver. The variable-gain amplifier (VGA) proposed consists of a digital control block, an auxiliary pair to retain a constant current density, and offers a gain-independent bandwidth (BW). A novel cell structure is designed for high gain, high BW, low power consumption and low Noise Figure (NF). The Heuristic Method is used to optimize the proposed circuit performance for high gain, low noise and low power consumption. This circuit is implemented and simulated using device-level description of TSMC 0.18[Formula: see text][Formula: see text]m CMOS process. Simulation results show that the DVGA can provide a gain variation range of 54[Formula: see text]dB (from 54[Formula: see text]dB to 0[Formula: see text]dB) with a 3[Formula: see text]dB BW over more than 110[Formula: see text]MHz. The circuit consumes the maximum power of 0.65[Formula: see text]mW from a 1.8[Formula: see text]V supply.

An Accurate dB-Linear CMOS VGA Based on Double Duplicate Biasing Technique

In this letter, a variable-gain amplifier (VGA) cell with an accurate dB-linear characteristic is proposed. By adopting a double-duplicate-biasing technique, this VGA cell achieves simple but effective continuous dB-linear gain control. The VGA cell features wide bandwidth, small chip area, and low power consumption. Based on the proposed VGA cell, we implement a fully differential three-stage VGA with dc-offset cancellation. This three-stage VGA is fabricated in a 0.13- ${\mu }\text{m}$ CMOS technology with a core area of 0.1 mm2. The measurement result shows the proposed dB-linear VGA presents gain-tuning range from −21 dB to 20 dB with dB-linear error of about 0.6 dB. At the maximum gain setting, an output ${P_{1{\mathrm{dB}}}}$ of −12 dBm and a noise figure of 27 are measured. The −3-dB bandwidth of the VGA is 580 MHz, and the core circuit consumes about 4.15 mA from a single 1.2-V supply.

A Control and Detecting System of Micro-Near-Infrared Spectrometer Based on a MOEMS Scanning Grating Mirror.

Based on the scanning grating mirror we developed, this paper presents a method of the precise control of a scanning grating mirror and of high-speed spectrum data detection. In addition, the system circuit of the scanning grating mirror control and spectrum signal detecting is designed and manufactured in this paper. The mirror control system includes a drive generator module, an amplitude detection module, a feedback control module, and a variable gain amplification (VGA) module; the detecting system includes a field programmable gate array (FPGA) main control module, a synchronous trigger module, an analog-digital conversion (ADC) module, and a universal serial bus (USB) interface module. The final results of the experiment show that the control system has successfully realized the precision control of the swing of the scanning grating mirror and that the detecting system has successfully realized the high-speed acquisition and transmission of the spectral signal and the angle signals. The spectrum has been reconstructed according to the mathematical relationship between the wavelength λ and the angle β of the mirror. The resolution of the spectrometer reaches 10 nm in the wavelength range of 800–1800 nm, the signal-to-noise ratio (SNR) of the spectrometer is 4562 at full scale, the spectrum data drift is 0.9% in 24 h, and the precision of the closed loop control is 0.06%.

Highly Linear and Reconfigurable Three-Way Amplitude Modulation-Based Mixerless Wireless Transmitter

A novel transmitter architecture that uses only envelope modulators is proposed. The complex baseband signal is decomposed into components using a three-coordinate decomposition technique. The individual components are translated to RF using three variable gain amplifiers (VGAs), which act as envelope modulators. The outputs of the VGAs are combined to generate the complex modulated RF signal. The proposed architecture does not have any phase modulator circuit and avoids phase noise and bandwidth expansion issues associated with polar topologies. This architecture avoids the use of any mixers or quadrature up-converters for frequency up-conversion. Accordingly, spurs that are associated with mixer circuits are avoided and, hence, no filtering is needed at the RF output of the transmitter. As RF filters are absent, this architecture offers wider RF bandwidth and would improve the design reconfigurability and integration capability. The signal at the output of the amplitude modulation-based transmitter has distortion due to gain and phase nonlinearity in the VGAs. A new memory polynomial-based modeling approach is used to linearize the transmitter. The performance of the implemented transmitter is evaluated using Long Term Evolution (LTE) signals and the measured error vector magnitude (EVM) and the adjacent channel leakage-power ratio (ACLR) are used to assess the signal quality. The measured EVM of the LTE signal of 1.4 MHz bandwidth, improved from 15% to 0.5% using digital predistortion technique, while the obtained ACLR is 54 dBc.

100 Gb/s Differential Linear TIAs With Less Than 10 pA/ $\sqrt {\mathrm {Hz}}$ in 130-nm SiGe:C BiCMOS

The design methodology and circuit implementation of a transimpedance (TI) amplifier (TIA) featuring low averaged input-referred current noise density without compromising the TIA bandwidth (BW) are presented. The technology role in the key performance metrics is also discussed and verified by means of two analogous TIA designs implemented in two different 130-nm SiGe:C BiCMOS processes from IHP, SG13S with $f_{T}/f_{\max }= 250/340$ GHz and SG13G2 with $f_{T}/f_{\max }= 300/500$ GHz. Both TIAs adopt a fully differential linear architecture with three stages: an input shunt-feedback TI stage followed by a variable gain amplifier which provides post-amplification with 15-dB gain control range and an output 50- $\Omega $ buffer. The TIA in SG13S features 68.5 dB $\Omega $ differential TI gain, 42-GHz 3-dB BW, and 8 pA/ $\sqrt {\mathrm {Hz}}$ averaged input-referred current noise density while the second TIA in SG13G2 provides 65 dB $\Omega $ differential TI gain, 66-GHz 3-dB BW, and 7.6 pA/ $\sqrt {\mathrm {Hz}}$ . Measured total harmonic distortion in both TIAs in the maximum gain condition is better than 5% for ~800 mVppd output swing and input currents of ~300 $\mu $ App. Both circuits dissipate 150 mW of power and are shown to operate at up to 100 Gb/s data rate with clean PRBS31 non-return to zero and PAM-4 eye diagrams. To the author’s best knowledge, the reported TIAs exhibit the lowest averaged input-referred current noise density shown to date at a BW sufficient to support 100 Gb/s net data rate, surpassing other silicon-based and InP implementations toward the next-generation 400 Gb/s optical links.

Compact and Wideband MMIC Phase Shifters Using Tunable Active Inductor-Loaded All-Pass Networks

To address the challenging needs of small size, wide bandwidth, and low-frequency applicability, a novel phase shifter implementation is introduced that utilizes tunable active differential inductors within all-pass networks. The inductor tuning is used to achieve phase shifts up to 180°. A switchable active balanced-to-unbalanced transition (balun) circuit is included in front of the all-pass network to complement its phase shift capability by another 180°. In addition, the all-pass network is followed by a variable-gain amplifier to correct for gain variations among the phase shifting states and act as an output buffer. Although active inductors have previously been used in the design of various components, to the best of our knowledge this is the first time that they have been used in an all-pass phase shifter. The approach is demonstrated with an on-chip design and implementation exhibiting wideband performance for S- and L-band applications by utilizing the 0.5- $\mu \text{m}$ TriQuint pHEMT GaAs monolithic microwave integrated circuits (MMIC) process. Specifically, the presented phase shifter $1 \times 3.95~ \text {mm}^{2}$ die area and operates within the 1.5–3-GHz band (i.e., 2:1 bandwidth) with 10-dB gain, less than 1.5-dB root-mean-square (rms) gain error and less than 9° rms phase error. Comparison with the state-of-the-art MMIC phase shifters operating in S- and L-bands demonstrates that the presented phase shifter exhibits a remarkable bandwidth performance from a very compact footprint with low-power consumption. Consequently, it presents an alternative for the implementation of wideband phase shifters where all-passive implementations will consume expensive die real estate.

A Low-Power Wideband dB-Linear Variable Gain Amplifier With DC-Offset Cancellation for 60-GHz Receiver

This paper presents a two-channel (I+Q) variable gain amplifier (VGA) for low power 60-GHz wireless receiver. The VGA consists of four-stage gain cells, an efficient DC-offset cancelling circuit and an output buffer for test purposes. To achieve wide bandwidth and low power consumption, a modified Cherry—Hooper amplifier gain cell is used. With a tunable transistor and its parasitic capacitance, a dB-linear characteristic and a flat gain response are achieved without any additional exponential circuit. The DC-offset is cancelled effectively with two proposed feedback loops. The measurement results show that the VGA achieves a gain range of 6 to 44 dB, an OP1dB of 1 dBm, and a 3-dB bandwidth of over 1 GHz with an excellent flat gain response. Fabricated in a 65-nm CMOS technology, the two-channel VGA core occupies a silicon area of only 0.055 mm2 and consumes only 10 mA from a 1.2 V power supply.

A 5-Gb/s 66 dB CMOS Variable-Gain Amplifier With Reconfigurable DC-Offset Cancellation for Multi-Standard Applications

This paper proposes a variable gain amplifier (VGA) with reconfigurable DC-offset cancellation (DCOC) for multi-standard applications. In this design, a cell-based design method and some bandwidth extension technologies are adopted to achieve a high data rate and a wide gain control range simultaneously. In addition, the DCOC having a tunable lower-cutoff frequency can make an optimum compromise between BER and SNR according to the specified baseband standard. The measurements show that the VGA achieves a gain control range from −6 dB to 60 dB, a bandwidth beyond 3 GHz, and a tunable lower-cutoff frequency from 0 to 300 kHz. When entering a 223−1 pseudo-random bit sequence signal at 5 Gb/s, the VGA consumes 17 mW from a 1.2-V supply and the output data peak-to-peak jitter is less than 40 ps. The VGA is fabricated in a 90-nm CMOS process with a chip size (including all pads) of $0.52\times0.5$ mm2.

A DC-2.5 GHz high linearity CMOS attenuator in a 0.18µm technology

A CMOS attenuator with high linearity has been designed and measured in a 0.18-µm CMOS process, to be used for a variable gain amplifier of RF wireless transceiver. The design is based on four cascaded Bridge-T attenuator stages that are consecutively activated to adjust the attenuation level and improve linearity. The design operates in the frequency band of DC-2.5 GHz with 2 - 3.5 dB insertion loss and 14 dB maximum attenuation in the entire frequency range. Measured and simulated results are in good agreement over the frequency band of interest. Measured worst case S11 and S22 are –10 and -8.8 dB, respectively, across the frequency band. The measured 1-dB compression point is +22 dBm at maximum-attenuation.

Indium–gallium–zinc–oxide thin-film transistor with a planar split dual-gate structure

An amorphous indium–gallium–zinc–oxide (a-IGZO) thin-film transistor (TFT) with a planar split dual gate (PSDG) structure has been proposed, fabricated and characterized. Experimental results indicate that the two independent gates can provide dynamical control of device characteristics such as threshold voltage, sub-threshold swing, off-state current and saturation current. The transconductance extracted from the output characteristics of the device increases from [Formula: see text] to [Formula: see text] for a change of control gate voltage from −2 V to 2 V, and thus the device could be used in a variable-gain amplifier. A significant advantage of the PSDG structure is its flexibility in controlling the device performance according to the need of practical applications.

Application of automatic gain control for radiometer diagnostic in SST-1 tokamak.

This paper describes the characterisation of a negative feedback type of automatic gain control (AGC) circuit that will be an integral part of the heterodyne radiometer system operating at a frequency range of 75-86 GHz at SST-1 tokamak. The developed AGC circuit is a combination of variable gain amplifier and log amplifier which provides both gain and attenuation typically up to 15 dB and 45 dB, respectively, at a fixed set point voltage and it has been explored for the first time in tokamak radiometry application. The other important characteristics are that it exhibits a very fast response time of 390 ns to understand the fast dynamics of electron cyclotron emission and can operate at very wide input RF power dynamic range of around 60 dB that ensures signal level within the dynamic range of the detection system.

A 64-Gb/s 1.4-pJ/b NRZ Optical Receiver Data-Path in 14-nm CMOS FinFET

A 64-Gb/s high-sensitivity non-return to zero receiver (RX) data-path is demonstrated in the 14-nm-bulk FinFET CMOS technology. To achieve high sensitivity, the RX incorporates a transimpedance amplifier whose gain and bandwidth are co-optimized with a 1-tap decision feedback equalization (DFE). The DFE, which operates at quarter-rate, features a look-ahead speculation to relax DFE timing to 4 unit-interval. The analog front end includes a transadmittance transimpedance inductorless variable gain amplifier, resulting in a low power and compact front end. The RX, wirebonded to a discrete GaAs photodiode, achieves an energy efficiency of 1.4 pJ/bit and −5-dBm optical modulation amplitude while recovering PRBS-7 data (bit-error-rate $ ) modulated by a VCSEL driver with a 2-tap feed forward equalization (FFE) (main + precursor) over 7 m of graded-index 50/125- $\mu \text{m}$ multimode fiber. The measured sensitivities at 56 and 32 Gb/s are −9- and −13-dBm optical modulation amplitude, respectively.