Equivalent Oxide Thickness Values Research Articles

Effects of pre- and post-microwave annealing treatments on pGe MOS device

Effects of pre- and post- microwave annealing (MWA) treatment on electrical characteristics of p-type Ge substrate (pGe) metal-oxide-semiconductor (MOS) devices were investigated in this work. The physical mechanism was studied with an X-ray photoelectron spectroscopy analysis. The pre-MWA treatment, which is similar to conventional post oxidation annealing on interfacial layer (IL), can passivate the oxygen vacancy by chemisorbed oxygen. The excess chemisorbed oxygen atoms may be left at the interface between IL and high-k, which would induce more interface/oxide traps and form more unstable components in IL. The chemisorbed oxygen can be replaced with well-bonded oxygen by using a post-MWA treatment on high-k dielectric , instead of a conventional post deposition annealing. As a result, pGe MOS device with a double-MWA treatment exhibits low equivalent oxide thickness value (~0.65 nm), small frequency dispersion, low interface trap density, and excellent reliability characteristics without increasing the leakage current. The oxygen vacancy passivation and chemisorbed oxygen suppression with a double-MWA treatment are crucial for high performance Ge MOS device and monolithic 3D IC applications. • The effect of pre- and post- microwave annealing (MWA) treatment is compared. • Oxygen vacancy can be passivated by chemisorbed oxygen in pre MWA. • Excess chemisorbed oxygen can be replaced with well-bonded oxygen by post MWA. • A p-type Ge substrate capacitor can be improved by double MWA.

Artificial Neural Network and Genetic Algorithm Based Hybrid Intelligence for Performance Optimization of Novel Inverted Funnel Shaped Fin Shaped Field Effect Transistor with Gate Stack High-k Dielectric

Today, Fin shaped Field Effect Transistors (FinFETs) are the foundation of the sub-nanometer technology node. The semiconductor industry endorses it in low-power (LP) and high-performance (HP) applications due to its better electrostatic control and exceptional scalability. In this paper, the structure of an inverted funnel-shaped FinFET device with a high-k stacked gate has been optimized using integrated Artificial Neural Network (ANN) and genetic algorithm (GA) approach. The comparative analysis of rectangular FinFET, trapezoidal FinFET and proposed novel shaped FinFET has also been explored. The electrical and analog performance parameters of the novel device present better performance results with respect to the other two transistors. In ANN training, the three datasets have been created by varying the metrics such as equivalent oxide thickness (EOT) and dielectric constant (k) of novel shaped FinFET device in Technology computeraided design simulator (TCAD). The amalgamation technique of ANN and GA optimization provides diminished Subthreshold Swing (SS), reduced off-current (IOFF), enhanced on-current (ION) and improved current ratio (ION/IOFF) corresponding to the optimal value of EOT and k. The new structure designed and simulated with the optimal amount of EOT and k results in outstanding performance parameters. The device metrics values, SS of 62.1 mV/dec, IOFF of 6.56×10-11, ION of 3.938×10-5 and ION/IOFF of 5.95×105 indicate that optimized device has suppressed Short Channel Effects (SCEs). The average deviatION of 3.48% between the value of ANN-GA optimized results obtained through MATLAB and TCAD simulated performance parameters justify the effectiveness of proposed FinFET.

High-k HfxZr1-xO₂ Ferroelectric Insulator by Utilizing High Pressure Anneal

In this article, we report the fabrication of Zr-rich high-k ferroelectric hafnium zirconium oxide (HZO) capacitor with TiN as the top and bottom electrodes demonstrating an equivalent oxide thickness (EOT) of 5.7 Å and remanent polarization (Pr) of ~16 μC/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . High-k-value and low EOT was achieved by utilizing multiphase region of HZO as well as high pressure post metallization annealing (HPPMA). Despite the high-k value of Zr-rich HZO films, the emergence of multiphase region at higher physical-thickness when annealed using rapid thermal annealing (RTA) limits its EOT value. On the contrary, multiphase emerges at a smaller physical thickness in HPPMA due to the formation of more o-phase as revealed by grazing incidence X-ray diffractometer (GIXRD). The smaller physical thickness of HPPMA together with the demonstration of significantly higher dielectric constant (>50) by HZO in the vicinity of multiphase, was therefore, found to be very effective in reducing the EOT.

Enhanced zirconia oxide dielectric quality of germanium p-channel metal oxide semiconductor field effect transistor by in-situ low temperature treatment in atomic layer deposition process

The gate dielectric quality of germanium (Ge) p-channel metal oxide semiconductor field effect transistor (MOSFET) is enhanced by using an in-situ low temperature treatment in atomic layer deposition (ALD) process in this work. With additional oxygen flow or remote oxygen-based plasma, the dangling bond, oxygen vacancy, and oxide traps in the ALD-formed zirconia oxide gate dielectric can be effectively passivated. Unlike the traditional post deposition annealing process that generally causes an increased equivalent oxide thickness (EOT) significantly, the in-situ low temperature treatment can lower the EOT value, reduce the gate leakage current, and improve the gate dielectric quality at the same time. As a result, the sample with an additional oxygen gas flow can exhibit a lower hysteresis value, better frequency dispersion characteristics, higher on/off current ratio, lower sub-threshold swing value, higher transconductance value, higher field effect mobility value, and better uniformity, simultaneously. This dielectric quality enhancement technique with in-situ low temperature process is promising to overcome the trade-off between EOT and gate leakage for the future Ge MOSFET devices.

Improved Device Characteristics Obtained Using a Novel High-K Dielectric Stack for 4H-SiC n-IGBT: HfO&lt;sub&gt;2&lt;/sub&gt;-SiO&lt;sub&gt;2&lt;/sub&gt;- AlN

We report on a novel method of stacking multiple oxide layers on 4H-SiC 20 kV IGBT. Instead of SiO2/SiC interface which is common for any SiC based MOS device, we found that the AlN/SiC interface would yield better results. We have performed 2D numerical simulations to analyze static characteristics for three combinations of dielectric stacks on IGBT: HfO2-SiO2, HfO2-AlN, and HfO2-SiO2-AlN (by maintaining the same equivalent oxide thickness value). In addition to higher transconductance (gm) and lower subthreshold swing (SS), the device with AlN/SiC interface offer comparatively lower RSP,ON and higher mobility with respect to temperature. Nevertheless, with a partial compromise on device characteristics improvement, insertion of SiO2 in the dielectric stack helps in suppressing the subthreshold current owing to higher band offset with respect to SiC. The turn off characteristics of the device is analysed using a clamped inductive circuit. Device with AlN/SiC has shown better dIc/dt and fall time compared to SiO2/SiC interface.

Structural and electrical characterization of multilayer Al2O3/ZnO nanolaminates grown by atomic layer deposition

Nanolaminates formed by several bilayers of Al2O3 and ZnO (AZA), grown by atomic layer deposition from Trimethyl aluminum, Diethyl zinc and water as co-reactants, were deposited on n-type (100) silicon substrates. A set of 5 nanolaminates with a total thickness of about 100nm, containing several Al2O3/ZnO bilayers with thicknesses of 0.28, 0.38, 2, 10 and 20nm, were prepared. XRD shows an evolution from amorphous to crystalline structure as a function of bilayer thickness. Capacitance-Voltage (C-V) and Current-Voltage (I-V) electrical characterization was carried out in order to evaluate the potential of the nanolaminates for microelectronic applications. Dielectric constant values between 8.3 and 9.6 were obtained, depending on bilayer thickness. The MOS capacitors exhibited net equivalent oxide thickness values between 44 and 38nm.

Reliability of Post Plasma Oxidation Processed ALD Al2O3/Hf1-xZrxO2 Thin Films on Ge Substrates

Germanium devices are widely investigated due to their high hole and electron mobility compared to that of silicon. Mobility above 300 cm2V-1s-1 has been reported for Ge PMOS. On the other hand, Ge NMOS showed poor drive current and low mobility in previous studies. This poor performance is attributed to the inability to form a good Ge/high-k interface (1). They also exhibit hysteresis during the capacitance voltage (C-V) sweep because of the presence of slow trap states near the dielectric substrate interface (2). Recently, the use of a slot-plane-antenna (SPA) Ar plasma during the deposition of ALD Hf1-xZrxO2 on Si substrate was reported to enhance the EOT (equivalent oxide thickness) downscaling potential with a suppressed trap formation in the bulk oxide under electrical stress (3). In this work, we have investigated TiN/HfZrO/Al2O3/Ge gate stack using MOS capacitors with six different Zr/(Hf+Zr) content (0%, 25%, 33%, 50%, 75%, and 100%) in the dielectrics. The dielectrics were subjected to SPA plasma oxidation after the deposition process. Electrical characterization of these devices was studied in order to observe the impact of Zr addition in HfO2. The equivalent oxide thickness (EOT), flat-band voltage (VFB), interface state density (Dit), C-V hysteresis, and leakage current (I-V) behavior were analyzed. Figure 1 shows the comparison of EOT and VFB as a function of Zr content in the dielectrics. Figure 2 presents the C-V hysteresis data (to the left axis) and mid gap Dit (to the right axis) for these devices. The addition of Zr in HfO2 was found to enhance the EOT up to 75% Zr incorporation. These devices also showed lower hysteresis in the C-V characteristics. However, A reduction in EOT for these devices showed to increase the flat-band voltage shift (Fig. 1). While devices with 100% Zr showed the highest EOT value coupled with the lowest mid gap Dit, a reduction in EOT with Zr addition in HfO2 moderately increases the Dit (Fig. 2 to the right scale). Figure Captions: Fig. 1: Equivalent oxide thickness (filled squares to the right scale) and flat-band voltage (open triangles to the left scale) comparison for the addition of Zr in HfO2. Fig. 2: Hysteresis behavior extracted from C-V sweep first from accumulation to inversion and then from inversion to accumulation (filled squares to the left scale) and interface state density by conductance method (open circles to the right scale) for ALD Hf1-xZrxO2/Al2O3 gate stacks on Ge substrate.

(Invited) Epitaxial Oxides on Silicon for CMOS and Beyond

A very promising way to realize advanced future devices is using single-crystalline, closely lattice matched oxides, which will be grown on the substrate of choice. The ability to integrate crystalline metal oxide dielectric layers into silicon structures can open the way for a variety of novel applications which enhances the functionality and flexibility ranging from high-K replacements in future MOS devices to oxide/silicon/oxide heterostructures for nanoelectronic application in quantum-effect devices. We present results for crystalline gadolinium oxides on silicon in the cubic bixbyite structure grown by solid source molecular beam epitaxy. This material has a large band gap of about 6 eV and nearly symmetrical band offsets as well as a low lattice mismatch of about -0.4 % to Si. Layers grown by an optimized process display a sufficiently high-K value to achieve equivalent oxide thickness values below 1 nm, combined with ultra-low leakage current densities, good reliability, and high electrical breakdown voltage. A variety of MOS devices has been fabricated based on these layers. The dielectric properties of such oxides are sensitive to small variations in structure and symmetry. It is known that thin layers of crystalline rare earth oxides can exhibit significant larger dielectric constants compared to bulk materials. For example, thin crystalline Gd2O3 films epitaxially grown on silicon exhibit dielectric constants up to 25 although the known bulk value is only around 13. The reason for that “enhancement effect” is not fully understood yet. As model systems, we chose Gd2O3 and Nd2O3 having very similar bulk dielectric constants and band gaps. The crystalline structures are also identical. On the other hand, the lattice spacing in Nd2O3 is larger while that of Gd2O3 smaller than the lattice spacing in silicon; i.e. one layer should be under compressive strain and the other under tensile strain. First, we will report on the dependence of the dielectric constant on layer thickness for epitaxial Gd2O3 on Si(111). The K-value strongly decreases with increasing layer thickness and reaches the bulk value at around 8 nm. Controlling the oxide composition in ternary (Gd1-xNdx)2O3 thin films enables us to tune the lattice mismatch to silicon, and thus the strain-induced variation in the dielectric constants of the layer from 13 (close to the bulk value) up to 20. Finally, we will show that solely tetragonal distortion of the cubic lattice is not sufficient to explain the huge lattice-mismatch induced enhancement in K-values. Thus, we will explain these effects by more severe strain induced structural phase deformations. Further, dielectric properties of epitaxial oxide thin films grown on Si have been found to improve significantly by incorporation of suitable dopants. We observe substantial reduction of the leakage current density in nitrogen-doped Gd2O3 layers. To achieve optimum electrical properties from such doped oxides it is important to understand the correlation between doping and the electronic structure of the material. X-ray photoelectron spectroscopy investigations revealed band gap narrowing in epitaxial Gd2O3 due to nitrogen doping, which leads to reduction in the valence band offset to Si. The observed reduction of the leakage current densities in the these layers with increasing nitrogen content suggests that nitrogen doping can be an effective route to eliminate the adverse effects of the oxygen vacancy induced defects in the oxide layers. We will finally demonstrate different approaches to grow Si nanostructures embedded into crystalline rare earth oxides. By efficiently exploiting the growth kinetics one could create nanostructures exhibiting various dimensions, ranging from three dimensionally confined quantum dots to the quantum wells, where the particles are confined in one of the dimensions. Double-barrier structures comprising epitaxial insulator as barriers and Si as quantum-well are attractive candidate for resonant tunneling devices. Embedded Si quantum dots (with average sizes below 5 nm) exhibit excellent charge storage capacity with competent retention and endurance characteristics suitable for nonvolatile memory device applications.

Structural and Electrical Properties of EOT HfO2 (

We report on changes in the structural, interfacial, and electrical characteristics of sub-1 nm equivalent oxide thickness (EOT) HfO2 grown on InAs by atomic layer deposition. When the HfO2 film was deposited on an InAs substrate at a temperature of 300 °C, the HfO2 was in an amorphous phase with an sharp interface, an EOT of 0.9 nm, and low preexisting interfacial defect states. During post deposition annealing (PDA) at 600 °C, the HfO2 was transformed from an amorphous to a single crystalline orthorhombic phase, which minimizes the interfacial lattice mismatch below 0.8%. Accordingly, the HfO2 dielectric after the PDA had a dielectric constant of ∼24 because of the permittivity of the well-ordered orthorhombic HfO2 structure. Moreover, border traps were reduced by half than the as-grown sample due to a reduction in bulk defects in HfO2 dielectric during the PDA. However, in terms of other electrical properties, the characteristics of the PDA-treated sample were degraded compared to the as-grown sample, with EOT values of 1.0 nm and larger interfacial defect states (Dit) above 1 × 10(14) cm(-2) eV(-1). X-ray photoelectron spectroscopy data indicated that the diffusion of In atoms from the InAs substrate into the HfO2 dielectric during the PDA at 600 °C resulted in the development of substantial midgap states.

ALD Hf0.2Zr0.8O2and HfO2with cyclic annealing/SPA plasma treatment: reliability

The reliability of atomic layer-deposited Hf0.2Zr0.8O2and HfO2on a SiON interfacial layer (IL) with cyclic deposition and annealing (DADA) and cyclic deposition and slot-plane-antenna Ar plasma exposure (DSDS) is studied. The results are compared with control, that is, As-Deposited samples, without any treatment during or after the dielectric deposition. DSDS Hf0.2Zr0.8O2demonstrates a promising equivalent oxide thickness (EOT) downscaling ability, a reduced gate leakage current, and low mid-gap interface state density as compared to the control device, while DADA Hf0.2Zr0.8O2has degraded the value of EOT as well as a degraded interface. When devices are subjected to a constant voltage stress in the gate injection mode, DSDS Hf0.2Zr0.8O2showed a four times reduction in the flat-band voltage shift and a three order of magnitude reduction in the stress-induced leakage current within 100-s stress as compared to the control sample. The observed time to failure, T63%, is the highest for DSDS Hf0.2Zr0.8O2. The addition of Zr and the cyclic plasma exposure (DSDS process) seems to supress the oxide trap formation in Hf0.2Zr0.8O2films. When DSDS Hf0.2Zr0.8O2deposited on two different ILs, SiON and plasma oxynitride are compared, in that SiON demonstrates improved reliability as compared to plasma oxynitride.

Influence of ultra-thin TiN thickness (1.4 nm and 2.4 nm) on positive bias temperature instability (PBTI) of high-k/metal gate nMOSFETs with gate-last process**Project supported by the National High Technology Research and Development Program of China (Grant No. SS2015AA010601) and the National Natural Science Foundation of China (Grant Nos. 61176091 and 61306129).

The positive bias temperature instability (PBTI) degradations of high-k/metal gate (HK/MG) nMOSFETs with thin TiN capping layers (1.4 nm and 2.4 nm) are systemically investigated. In this paper, the trap energy distribution in gate stack during PBTI stress is extracted by using ramped recovery stress, and the temperature dependences of PBTI (90 °C, 125 °C, 160 °C) are studied and activation energy (Ea) values (0.13 eV and 0.15 eV) are extracted. Although the equivalent oxide thickness (EOT) values of two TiN thickness values are almost similar (0.85 nm and 0.87 nm), the 2.4-nm TiN one (thicker TiN capping layer) shows better PBTI reliability (13.41% at 0.9 V, 90 °C, 1000 s). This is due to the better interfacial layer/high-k (IL/HK) interface, and HK bulk states exhibited through extracting activation energy and trap energy distribution in the high-k layer.

Sub-0.5 nm equivalent oxide thickness scaling for Si-doped Zr1-xHfxO2 thin film without using noble metal electrode.

The dielectric properties of the Si-doped Zr1-xHfxO2 thin films were investigated over a broad compositional range with the goal of improving their properties for use as DRAM capacitor materials. The Si-doped Zr1-xHfxO2 thin films were deposited on TiN bottom electrodes by atomic layer deposition using a TEMA-Zr/TEMA-Hf mixture precursor for deposition of Zr1-xHfxO2 film and Tris-EMASiH as a Si precursor. The Si stabilizer increased the tetragonality and the dielectric constant; however, at high fractions of Si, the crystal structure degraded to amorphous and the dielectric constant decreased. Doping with Si exhibited a larger influence on the dielectric constant at higher Hf content. A Si-doped Hf-rich Zr1-xHfxO2 thin film, with tetragonal structure, exhibited a dielectric constant of about 50. This is the highest value among all reported results for Zr and Hf oxide systems, and equivalent oxide thickness (EOT) value of under 0.5 nm could be obtained with a leakage current of under 10(-7) A·cm(-2), which is the lowest EOT value ever reported for a DRAM storage capacitor system without using a noble-metal-based electrode.

Effect of Al Doping on the Reliability of ALD HfO2

CMOS device scaling below the 22 nm technology node requires gate dielectric materials with superior properties to those of conventional high-k materials. It was found that, Al incorporation into HfO2 results in an increase in the transition temperature from amorphous to polycrystalline state (1-2). Improved thermal stability (2) and enhanced permittivity (3) by Al doping into ALD HfO2 was also reported. As a result of the improvement in film properties, improved equivalent oxide thickness (EOT) values, reduced gate leakage current, lower hysteresis and improved interface quality were also observed for Al doped HfO2 (4-6). However, intermixing of HfO2 and Al2O3 depends significantly on the stack structure, which results in variations in the stoichiometry in the film (7). The relative position of HfO2 and Al2O3 in HfO2/Al2O3bi-layer has a significant influence on positive charge formation in the dielectrics and also on the quality of the interfacial layer (IL) (8-10).In this work, we deposited and studied the reliability of 40 cycles ALD HfO2 doped with Al in the deposition process. The ALD thin film composition was measured by X-ray photoelectron spectroscopy (XPS). Thin films with Al/(Al+Hf)% composition ranging 0% to 8% were deposited and annealed at 800oC in N2 ambient. MOS capacitors were then fabricated with ALD TiN as the metal gate. The electrical measurements show that, devices with ~2% Al/(Hf+Al)% have an optimized performance with 17% lower EOT than undoped HfO2. The amount of positive charge and gate leakage current density were also evaluated for all devices.The reliability of these devices was monitored by subjecting them to a constant field stress at E= 27.5 MV/cm in the gate injection mode, where the applied voltage to the gate was modified according to the EOT to have equal field across all the dielectrics. Stress-induced trap generation in the dielectrics was observed due to bulk and interface defects. Trap formation followed a power law function with stress time. Observed stress induced flat-band voltage shift (Fig. 1) shows that devices with Al/(Hf+Al)% =2% have 36% reduction in the rate of trap generation as compared to HfO2, whereas degraded flat-band voltage shift was observed for devices with Al/(Hf+Al)% =7%. It can be inferred that an optimized Al concentration in HfO2can lead to an improvement of the device performance. In order to further understand the reliability characteristics we plan to evaluate the change in interface state density with stress and their time dependent dielectric breakdown (TDDB) characteristics. References M.-Y. Ho et al., Appl. Phys. Lett., 81, 4218 (2002). H. Y. Yu et al., Appl. Phys. Lett., 81, 3618(2002). P. K. Park et al., Appl. Phys. Lett., 89, 192905(2006). W. J. Zhu et al., IEEE Electron. Dev. Lett., 23(11), 649(2002). V. Mikhelasvili et al., Appl. Phys. Lett., 85, 5950(2004).Y.-K. Chiou et al., J. Electrochem. Soc., 154 (4) G99(2007).M. H. Cho et al., Appl. Phys. Lett., 81, 1071(2002).B. H. Lee et al., Appl. Phys. Lett., 76, 1926 (2000).L. G. Gosset et al., J. Non-Cryst. Solids, 303, 17(2002).W. Wang et al., J. Appl. Phys., 105, 064108 (2009).

Reduction of silicon dioxide interfacial layer to 4.6Å EOT by Al remote scavenging in high-κ/metal gate stacks on Si

• Al diffusion into gate stack leads to EOT reduction. • Process reduces the EOT at low temperature (400 °C) and is suitable for replacement gate processes. • Extensive interface studies support the electrical measurements. • Reactions are in agreement with thermodynamical considerations. The continued device scaling demands the reduction of the equivalent oxide thickness (EOT) below 1 nm. For HfO 2 -based gate stacks, the interfacial SiO 2 limits the EOT scaling. A low EOT can only be achieved if the interfacial layer (IL) is reduced to its physical limit of ∼4 Å. Such thin EOT are achievable if redox reactions within the gate stack are employed in order to reduce SiO 2 . This study reports on the use of an Al layer in combination with a TiN metal electrode to reduce the IL and achieve lowest EOT values. The lowest EOT achieved was 4.6 Å. However, the scavenging process was found to strongly depend on the thermal budget after Al deposition. The presented process adapts a standard metal-inserted poly-Si flow (MIPS) prior to Al deposition, but may also be an option to control IL regrowth.

Characteristics of Gd2−xLaxO3 high-k films by metal-organic chemical vapor deposition

Gd 2− x La x O 3 high- k films were deposited on (1 0 0) Si substrates by low-pressure metal-organic chemical vapor deposition (MOCVD). The metal-organic precursors we used were Gd and La β-diketonates. The structure, band gap, composition and electrical properties of Gd 2− x La x O 3 films have been investigated. X-ray diffraction patterns show that as-deposited thick Gd 2− x La x O 3 films on Si have formed cubic phase of solid solution with (2 2 2) preferred orientation. The band gap of the Gd 2− x La x O 3 films can be calculated to be 5.78 eV using a UV–vis–NIR spectrophotometer. X-ray photoelectron spectroscopy depth profile analyses reveal that there exists an interfacial layer of Gd–La–Si–O silicate and the La element is rich in interfacial layer. The equivalent oxide thickness (EOT) of 1.08 nm has been obtained with the flatband voltage ( V fb ) of 1.0 V and leakage current density ( J A ) of 3 A/cm 2 at V g = V fb + 1 V for Gd 2− x La x O 3 ( x = 1.29) films of 8 nm physical thickness after 800 °C post-annealing. ► Gd 2− x La x O 3 high- k films were deposited on Si substrates by MOCVD. ► The structure, band gap, composition and electrical properties of Gd 2− x La x O 3 films have been investigated. ► The films have formed cubic phase of solid solution with (2 2 2) preferred orientation. ► Interfacial layer of the films is Gd–La–Si–O silicate and the La element is rich in interfacial layer. ► The EOT value of 1.08 nm is achieved. Gd 2− x La x O 3 high- k films were deposited on (1 0 0) Si substrates by low-pressure metal-organic chemical vapor deposition (MOCVD). The metal-organic precursors we used were Gd and La β-diketonates. The structure, band gap, composition and electrical properties of Gd 2− x La x O 3 films have been investigated. X-ray diffraction patterns show that as-deposited thick Gd 2− x La x O 3 films on Si have formed cubic phase of solid solution with (2 2 2) preferred orientation. The band gap of the Gd 2− x La x O 3 films can be calculated to be 5.78 eV using a UV–vis–NIR spectrophotometer. X-ray photoelectron spectroscopy depth profile analyses reveal that there exists an interfacial layer of Gd–La–Si–O silicate and the La element is rich in interfacial layer. The equivalent oxide thickness (EOT) of 1.08 nm has been obtained with the flatband voltage ( V fb ) of 1.0 V and leakage current density ( J A ) of 3A/cm 2 at V g = V fb + 1 V for Gd 2− x La x O 3 ( x = 1.29) films of 8 nm physical thickness after 800 °C post-annealing.

Deposition and characterization of MgO/Si gate stacks grown by molecular beam epitaxy

In this article, the deposition and characterization of amorphous MgO films grown on Si (001) using molecular beam epitaxy is reported. In order to ensure amorphous films, low substrate temperatures (200°C) and high oxygen pressures were used (up to 5×10−3Pa). Both atomic and molecular oxygen species were used at different pressures. Films ranging in thickness from 3nm till 30nm were grown and characterized using structural and electrical methods.The dielectric constant deduced from this thickness series corresponds to 8.74 close to the bulk value of 9.8. The best equivalent oxide thickness value observed for this series – grown under high oxygen pressure – corresponds to 1.2 nm for a current density measured at VFB−1V of 0.1A/cm2. The films grown with atomic oxygen display a lower capacitance and lower leakage compared to the films grown using molecular oxygen. This is due to the appearance of a thin SiO2 interface layer which is also responsible for the high defect density observed in the capacitance–voltage measurements. Upon annealing both types of films in forming gas for 15min at 450°C, the capacitance decreases further while the leakage increases. This change is assigned to the appearance of the lower bandgap (6.6eV), lower dielectric constant (6.6) phase of silicate, MgSiO3. Furthermore a VFB shift of −0.6V is observed and is related to the appearance of oxygen vacancies as Mg diffuses into the SiO2 interface layer.

Electrical properties of metal-ferroelectric-insulator-semiconductor structure with Lanthanum Dysprosium Oxide and SrBi2Ta2O9

layer was prepared. The LDO thin film and the SBT film were deposited by using the sol-gel method. The sol-gel-derived LDO thin films on Si had very flat and smooth surface morphologies. The equivalent oxide thickness (EOT) values were about 10.1 nm, 12.5 nm, and 12.8 nm for 750 C, 800 C, and 850 C, respectively. Also, the relative dielectric constants of the 750 C-annealed, 800 C-annealed and 850 C-annealed LDO films were about 15.4, 12.5, and 12.2, respectively. On the whole, the leakage current densities showed good characteristics regardless of the annealing temperature. Especially, the leakage current property of the 850 C-annealed LDO film was visibly superior to those of the others at voltages over 6 V. The C-V characteristics of the Au/SBT/LDO/Si structure showed clockwise hysteresis loops, and the memory window width increased as the bias

Characteristics of Hafnium Silicate Films Deposited on Si by Atomic Layer Deposition Process

We investigated the effects of annealing (i.e., temperature and time) on the characteristics of hafnium silicate () films deposited on a Si substrate by atomic layer deposition process (ALD). We found that the post deposition annealing under oxidizing ambient causes the oxidation of residual Hf metal components, resulting in the improvement of electrical characteristics (e.g., hysteresis window and leakage current are decreased). In addition, we observed the annealing temperature is more important than the annealing time for post deposition annealing. Based on these observations, we suggest that post deposition annealing under oxidizing ambient is necessary to improve the electrical characteristics of films deposited by ALD. However, the annealing temperature has to be carefully controlled to minimize the regrowth of interfacial oxide, which degrades the value of equivalent oxide thickness.

High temperature (1000 °C) compatible Y–La–Si–O silicate gate dielectric in direct contact with Si with 7.7 Å equivalent oxide thickness

Yttrium lanthanum silicate was formed in direct contact with silicon after a rapid thermal annealing at 1000 °C in metal-oxide-semiconductor capacitors leading to an equivalent oxide thickness (EOT) of 7.7 Å. This represents one of the lowest EOT value reported for a gate-first process with non Hf-based dielectric. The silicate is formed by interdiffusion of La2O3 and YOx layers and interfacial SiO2 consumption. Yttrium incorporation reduces the leakage current density as well as the large negative flatband voltage (Vfb) shift that is associated with lanthanide-based dielectrics. The Vfb value can be appropriately tuned for n-type field-effect transistor operation by changing the silicate composition.

Process Engineering and Trap Distribution for Dielectric/Si Interfacial Layer in High-k Gated MOS Devices

The effects of interfacial layer at high-k dielectric/Si substrate formed by using stress-relieved pre-oxide (SRPO) treatment on electrical characteristics of MOS devices were studied in this work. The equivalent oxide thickness value could be scaled with reducing the thickness of the high quality IL. The reliability in terms of stress-induced leakage and stress-induced Vfb shift is clearly improved for MOS device with a SRPO treatment. Besides, the constant-voltage stress-induced interface trap generation in MOSFET was measured by charge-pumping techniques. The influences of stress and recovery on devices with HfO2 high-k dielectric are also compared. Results show that the stress induced Vth shifts can be separated into two stages, namely, trap filling and generation. The trap generation stage is only determined by the stress voltage and temperature.