Value Change Dump Research Articles

A Multi-One Instruction Set Computer for Microcontroller Applications

This work presents a simple integer-only instruction set architecture and microarchitecture derived from One Instruction Set Computers (OISCs) and embedding multiple execution modes ( ${m}$ OISC), capable of running at a reasonable performance level to enable basic usability in microcontroller applications. The purpose of ${m}$ OISC is to enable simple data transfer tasks and run small programs while maintaining ultimate simplicity. We present the internal organization for a computer architecture including an 8bit I/O register, and 64kB central Random Access Memory (RAM), organized in two-bytes words. The processor can run code generated assuming an OISC or a Complex Instruction Set Computer (CISC) scheme (op-code based), depending on the programmer’s demands and based on the initial setting of a register during start-up. To enable practical applications and demonstrate successful exploitation of ${m}$ OISC in view of integration in a compiler back-end, we designed a custom Proof-of-Concept (PoC) software design toolchain based on LLVM and clang . Although not targeting all the features of commercial ISA, the toolchain is capable of compiling C code from LLVM intermediate representation or generating ${m}$ OISC code translated from ARM, x86, RISC-V, and MIPS assembly. The toolchain also enables practical Value Change Dump (VCD) simulations output with graphical plots of the CPU state and associated symbols. A PoC microcontroller system has been synthesized in a low power Field Programmable Gate Array (FPGA) and verified in a basic wireless telemetry application including a Synchronous Peripheral Interface (SPI) RFM9x Long RAnge (LoRA) transceiver and a MAX30205 Inter Integrated Circuit (I2C) temperature sensor, using its 8bit I/O port, with software bus interface implementation. ${m}$ OISC occupies ~6% of resources on a Cyclone 10LP FPGA, for 1397 Adaptive Look-Up Tables (ALUTs) and 461 dedicated logic registers. The measured dynamic current consumption of the complete FPGA board with synthesized ${m}$ OISC is 12mA at 100MHz clock.

PESL: System-Level Estimation of Power-Management Effect on Dynamic Energy Consumption

Power estimation is one of the key aspects that can help designers create digital circuits more effectively. If a designer is able to estimate circuit parameters during the early stages of development, correct decisions can be made that can significantly shorten the design time. The early design stages are represented by modeling at the system level of abstraction. However, existing system-level power/energy estimation methods are either too complicated, or they do not consider power management when estimating power consumption, meaning they are inaccurate. Therefore, in this paper we propose a method for a more accurate system-level estimation of the dynamic energy consumption by considering the impact of power management. The SystemC description of a power-managed system and the simulation results (in the form of the value change dump (VCD)) are inputs to the estimation method. The proposed method is based on an activity profile using the modified Hamming distance computation. The method is especially useful for the exploration of alternative power-management strategies, and it helps the designer to select the most efficient strategy.

Automated Nonintrusive Analysis of Electronic System Level Designs

Due to the ever increasing complexity of hardware systems, designers strive for higher levels of abstractions in the early stages of the design process. Modeling hardware at the electronic system level (ESL) is one way to address this demand, with the C++-based system modeling framework SystemC and its abstract communication library transaction level modeling (TLM) having become de-facto standards for ESL system design. While the C++ compiler is sufficient to compile and simulate a given ESL design, for tasks of design understanding, debugging, or validation (where access to the details of design’s structure and behavior is necessarily required), design needs to be processed by an appropriate tool. This problem is often solved by adding instrumentation code to either the design or the library, usually resulting in incomplete logs, work overhead and/or incompatibilities. This paper introduces an approach that automatically extracts information about both, structure and behavior of SystemC designs and TLM transactions, nonintrusively. The information is retrieved from a given design by running it in debug mode while being connected to a preprogrammed debugger, thus leaving the existing sources and workflows untouched while collecting a vast amount of data without user intervention. Illustrating use cases, value change dump files of the SystemC models’ behavior and unified modeling language activity diagrams of transaction protocols are created automatically from simulation runs.

Visualization of VHDL-based simulations as a pedagogical tool for supporting computer science education

Communication between information processing systems becomes a challenge, especially in the “big data” era. It is a mandatory subject in the topic “Architecture and organization” of the computer science curriculum. However, in our experience, it is a rather complex topic for students. Simulation visualization can be used to graphically illustrate various concepts of computer science. In this paper, we present the application of NICSim-vhd, which is an acronym for VHDL-based Network Interface Card simulation model, as a pedagogical tool for supporting undergraduate computer science students’ education. NICSim-vhd allows simulating the network-to-memory data path at a network node and generating Value Change Dump (VCD) files for simulation visualization of hardware description languages-based models. We provide a taxonomy of learner engagement with simulation visualization. Grounded in Bloom’s well recognized taxonomy of understanding, we suggest how to assess the learning outcomes to which such engagement may lead.

Mapping Based Energy Efficient Counter Design on FPGA

— In this work, 8-bit counter power optimized counter is designed with help of energy efficient techniques called mapping and simulation activity file in format of Value Change Dump (VCD) file and setting file (*.xpa) to define toggle rate, activity rate and enable rate for the power consumption estimation in order to get energy efficient design. With mapping, there is 33.33%, 34.61%, 36.5%, 36.49%, 36.86%, 36.9% dynamic power reduction in counter when device is operating on 10MHz, 100MHz, 1GHz, 10GHz, 100GHz and 1 THz frequency. This reduction achieved by mapping control signal to control port in place of mapping control signal to LUT (Look Up Table) input. In Resource utilization, when we are mapping the control signal to control port, there is 70.58% less number of LUT and 39.89% less number of IO usage than mapping the control signal to LUT inputs. Spartan-3 FPGA is taken as target device and Xilinx 14.1 ISE is taken as design, synthesis and implementation tools. Verilog HDL(Hardware Description Language) is used to synthesize the counter on FPGA. The power dissipation of the FPGA based energy efficient design is verified using Xilinx XPower tool.

ELEON3LP – Superscalar and low-power enhancements of single issue general purpose processor model

Low power consumption and high-performance are the most important factors in modern embedded System-on-Chip (SoC) designs. Increasing computation complexity and incessant growth of clock frequency reveals the necessity for dynamic and smart utilization of the available hardware resources. The paper presents the modified LEON3 processor IP core as an exemplary process of enhancing single issue general purpose processor with superscalar abilities and low-power features. The results of this work can be applied to many existing general purpose processor models to achieve low-power and high-performance systems suitable for modern embedded applications. In comparison with the original LEON3 IP core, the new one may execute up to two instructions per cycle and dynamically manage incorporated power domains. The Enhanced LEON3 IP core was synthesized for 500MHz using UMC 90nm CMOS technology. Performed gate level VCD-based (Value Change Dump) power estimation shows that combining superscalar and low-power techniques allows performing faster program execution with less energy consumption than the original design.

Optimisation of VCD Format and Testbench Reuse in Implementation of ASIC Tester

This paper presents a new methodology to re-use test-benches In FPGA/ASIC testing. The state-of-the art methodology uses hardware/software co-design. A platform is developed which combines the advantages of simulation & Automatic Test Equipment (ATE) using Reconfigurable Devices (RD) like FPGAs to verify the functionality of ASICs and RDs. The proposed testing environment consists of the FPGA based reconfigurable hardware and set of software tools to interface between a simulator and hardware environment. It is a standalone tool i.e. independent of any CAD development environment and runs from any PC with windows operating system. It takes in a test bench in Value Change Dump (VCD) format [1] and converts it to a set of test patterns, compatible with hardware.Software tool includes VCD to IOC (Input-Output Configuration), Signal replication and methodology of generating test patters. The testbench created by the designer is reused to create VCD file. The same is input as a test pattern for the Device Under Test (DUT) through ASIC Tester (AT). In the developed AT, VCD formats are modified, rather de-optimised in memory usage for hardware design simplicity and acceleration.The results obtained from DUT are compared with the simulation results obtained while designing RTL of the ASIC/FPGA for further fault analysis if any.