Abstract
This work presents a simple integer-only instruction set architecture and microarchitecture derived from One Instruction Set Computers (OISCs) and embedding multiple execution modes ( ${m}$ OISC), capable of running at a reasonable performance level to enable basic usability in microcontroller applications. The purpose of ${m}$ OISC is to enable simple data transfer tasks and run small programs while maintaining ultimate simplicity. We present the internal organization for a computer architecture including an 8bit I/O register, and 64kB central Random Access Memory (RAM), organized in two-bytes words. The processor can run code generated assuming an OISC or a Complex Instruction Set Computer (CISC) scheme (op-code based), depending on the programmer’s demands and based on the initial setting of a register during start-up. To enable practical applications and demonstrate successful exploitation of ${m}$ OISC in view of integration in a compiler back-end, we designed a custom Proof-of-Concept (PoC) software design toolchain based on LLVM and clang . Although not targeting all the features of commercial ISA, the toolchain is capable of compiling C code from LLVM intermediate representation or generating ${m}$ OISC code translated from ARM, x86, RISC-V, and MIPS assembly. The toolchain also enables practical Value Change Dump (VCD) simulations output with graphical plots of the CPU state and associated symbols. A PoC microcontroller system has been synthesized in a low power Field Programmable Gate Array (FPGA) and verified in a basic wireless telemetry application including a Synchronous Peripheral Interface (SPI) RFM9x Long RAnge (LoRA) transceiver and a MAX30205 Inter Integrated Circuit (I2C) temperature sensor, using its 8bit I/O port, with software bus interface implementation. ${m}$ OISC occupies ~6% of resources on a Cyclone 10LP FPGA, for 1397 Adaptive Look-Up Tables (ALUTs) and 461 dedicated logic registers. The measured dynamic current consumption of the complete FPGA board with synthesized ${m}$ OISC is 12mA at 100MHz clock.
Highlights
O NE Instruction Set Computers represent the ultimate simplicity in the implementation of calculators [1], [2]
Not targeting all the features of commercial ISA, the toolchain is capable of compiling C code from LLVM intermediate representation or generating mOISC code translated from ARM, x86, Reduced Instruction Set Computers (RISCs)-V, and MIPS assembly
A PoC microcontroller system has been synthesized in a low power Field Programmable Gate Array (FPGA) and verified in a basic wireless telemetry application including a Synchronous Peripheral Interface (SPI) RFM9x Long RAnge (LoRA) transceiver and a MAX30205 Inter Integrated Circuit (I2C) temperature sensor, using its 8 bit I/O port, with software bus interface implementation. mOISC occupies ∼6% of resources on a Cyclone 10LP FPGA, for 1397 Adaptive Look-Up Tables (ALUTs) and 461 dedicated logic registers
Summary
O NE Instruction Set Computers represent the ultimate simplicity in the implementation of calculators [1], [2]. The object of this work is to design a minimal but practically usable computer for basic microcontroller applications by extending OISCs. We present an ISA with an associated machine, named multiple One-Instruction Set Computer (mOISC, or dynamic RISC, dRISC, for similarity with ultimate RISC [2]) that can toggle among 14 run modes, each corresponding to a single OISC, with low resource occupation and based on a hybrid TTA/OISC scheme [25]. MOISC can execute different run modes based on the value of MCR, exec assumes different meanings, for instance, different OISC schemes such as subleq or addleq This way, by tolerating the overhead of writing to MCR the machine issues at all effects instructions of multiple types but it can work as an OISC by statically setting a machine code without changes. Machine registers are used to set and read the I/O port, its input-output direction, the internal clock speed of the machine, to stop the CPU while waiting for an I/O event on physical pins, and to read the last arithmetic comparison results between mem[a] and mem[b], including overflow status
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