UTBB Fully Depleted Silicon On Insulator Research Articles

Study on low rate of change characteristics of saturation output current of 28 nm UTBB FDSOI at 300 °C high-temperature

Partially-depleted silicon-on-insulator (PDSOI) MOSFETs with full dielectric isolation structure are widely used in the high temperature field of 225 °C, but affected by the threshold voltage and carrier mobility, the saturated output current has a rate of change as high as 24.9% at 25 °C–300 °C, which will reduce the working speed and accuracy of the analog circuit. This paper studies the high temperature output current characteristics of ultra-thin body and buried oxide (UTBB) fully-depleted silicon-on-insulator (FDSOI) MOSFETs with the 28 nm low voltage threshold structure. The experimental results show that when the gate voltage of the device is constant, the saturation current change of 28 nm short-channel FDSOI device is 1.93% in the temperature range from 25 °C to 300 °C, which is 12.9 times more stable than that of 0.13 μm PDSOI device, 4.5 times and 8.4 times higher than that of 0.3 μm and 2 μm long-channel FDSOI device. When the gate voltage of the device drifts from the zero-temperature coefficient (ZTC) point by ±10%–±20%, the output current change of the short-channel FDSOI device is still the lowest. It is proved by theory and simulation that the low temperature change rate of the carrier velocity of the short-channel FDSOI device is the main factor affecting the stability of the output current. From the analysis of the saturation current model and the ZTC operating point, reducing the gate operating voltage of the device or increasing the threshold voltage of the device can further improve the stability of the output current at high temperatures. The research in this paper proves that the 28 nm UTBB FDSOI device has good high temperature saturation current stability, which can well meet the output current stability requirements of high temperature analog circuits.

Impact of Aging Degradation on Heavy-Ion SEU Response of 28-nm UTBB FD-SOI Technology

Integrated circuits (ICs) are a keystone for most critical applications operating in high-level radiation environments, spanning from high-energy nuclear applications up to space applications. The long-term reliability of these applications is essential for safe operation. However, the radiation effects for ICs are commonly investigated using fresh circuits, leaving the coupled effect of radiation and aging degradation unknown. This article investigates the impact of negative bias temperature instability (NBTI) aging degradation mechanism on the heavy-ion single event upset (SEU) radiation susceptibility of 28-nm ultra-thin body and buried oxide (UTBB) fully depleted silicon on insulator (FD-SOI) technology using a custom-designed test vehicle. NBTI aging degradation mechanism has been experimentally proven to increase the SEU sensitivity up to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2\times $ </tex-math></inline-formula> for 28-nm UTBB FD-SOI flip-flops. A comprehensive framework is presented to analyze the underlying mechanisms for the impact of NBTI, which includes NBTI aging mechanism modeling, SEU SPICE simulation, TCAD irradiation simulation, and Monte-Carlo simulation of radiation effects. The framework offered a quantitative prediction of the effect of NBTI degradation mechanism on the heavy-ion SEU radiation sensitivity.

A Three-Stage Charge Pump With Forward Body Biasing in 28 nm UTBB FD-SOI CMOS

Energy harvesting techniques provide solutions for powering battery-free circuits or even for charging storage elements such as batteries or super capacitors. In this paper a self-starting switched-capacitor approach based on three-stage charge pump that is appropriate to thermoelectric and photo-voltaic energy harvesting, is carried out in a 28 nm ultra-thin buried oxide (UTBB) fully-depleted silicon-on-insulator (FD-SOI) CMOS technology. By taking advantage of the FD-SOI substrate characteristics, the forward-body-biasing (FBB) technique is applied in order to improve switch conductances. In addition, a sizing exploration of standard N-type and flipped-well P-type devices operating as switches is advanced, in order to provide optimum balance between their conductances. Extensive simulation results validate the proper operation of the charge pump at a minimum input voltage of 150 mV, and show a maximum efficiency peak of 63.3% at an input voltage of 350 mV and load a current of 500 nA.

Ultrahigh-Sensitive CMOS pH Sensor Developed in the BEOL of Standard 28 nm UTBB FDSOI

This paper reports ultrahigh-sensitive and ultralow-power CMOS compatible pH sensors that are developed in the back-end-of-line (BEOL) of industrial 28-nm ultrathin body and buried oxide (UTBB) fully depleted silicon-on-insulator (FDSOI) transistors. Fabricating the sensing gate and the control gate of the sensors in a capacitive divider circuit, CMOS compatible pH sensors are demonstrated where the front gate bias is applied through a control gate rather than a bulky reference electrode. On the other hand, the strong electrostatic coupling between the front gate and the back gate of FDSOI devices provide an intrinsic signal amplification feature for sensing applications. Utilizing an atomic layer deposited aluminum oxide (Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> ) as a pH sensing film, pH sensors having a sensitivity of 475 mV/pH and 730 mV/pH in the extended gate and BEOL configuration, respectively, are reported. Sensitivities of both configurations are superior to state-of-the-art low power ion-sensitive field-effect transistors. The small sensing area and the FDSOI-based low power technology of the device make the sensors ideal for the IoT market. The proposed approach has been validated by TCAD simulation, and demonstrated through experimental measurements on proof-of-concept extended gate pH sensors and on sensors that are developed in the BEOL of industrial UTBB FDSOI devices.

Characterization of RF Noise in UTBB FD-SOI MOSFET

In this paper, we report the noise measurements in the RF frequency range for ultrathin body and thin buried oxide fully depleted silicon on insulator (FD-SOI) transistors. We analyze the impact of back and front gate biases on the various noise parameters; along with discussions on the secondary effects in FD-SOI transistors which contribute to the thermal noise. Using calibrated TCAD simulations, we show that the noise figure changes with the substrate doping and buried oxide thickness.

(Invited) UTBB FDSOI PMOSFETs Including Strained SiGe Channels at the 14nm Technology Node and Beyond

The 28 nm Ultra-Thin Body and Buried Oxide (UTBB) Fully Depleted Silicon-On-Insulator (FDSOI) technology is in production [4]. This technology addresses both high performance and low power / low voltage applications. Indeed, a 28 nm FDSOI Processor (CPU) has been demonstrated to run at 3 GHz for a 1.3 V supply voltage (Vdd), 1 GHz for 0.6 V, still 300 MHz at 0.5 V [1]. This latter result evidences the high potential of FDSOI for Low Voltage operation, required for the next handheld, mobile or Internet-of-Things markets. The 14nm FDSOI technology extends this offer to even more performance (+50% frequency at a given dissipated power), with a 100mV supply voltage reduction [5]. For the 14nm FDSOI, we have integrated SiGe channel, which enables to achieve high biaxial compressive stress due to the lattice mismatch between Silicon and Germanium. The compressive stress enhance the hole mobility, and in turn pMOSFETs performance. In such an approach, one of the main challenges is to conserve the strain during the CMOS integration. Especially, it is well known that the patterning of SiGe leads to partial relaxation close to the active edges. This relaxation affects especially the level of stress in the channel when the dimensions of the active are small. The stress configuration becomes thus strongly layout-dependent. We have physically and electrically characterized the strain-induced layout effects in SiGe pMOSFETs built on Ultra-Thin-Body and Buried-Oxide Fully-Depleted-Silicon-On-Insulator (UTBB FDSOI). This layout effect is reproduced by an accurate physics-based electrical model, which enable us to predict the device and design performance for various technological configurations: germanium concentration in the channel, isolation and channel process integration. In order to mitigate the impacts of the SiGe channel relaxation, we have studied two kinds of solutions. First, technological solutions are possible, leading to +21% effective current increase in short transistor at Lg=20nm gate length and in turn -15% delay reduction for ring-oscillator of 1-gate finger inverters. Secondly, we demonstrate the benefits induced by smart design layouts, enabled by process integration goodies and some layout constructs. Especially, a continuous-RX design, which consists in a long active line configuration, optimizes the stress management, maintaining longitudinal stress component while relaxing the transverse one. A 28% ring oscillator delay improvement is experimentally demonstrated at same leakage for 1-finger inverter at VDD=0.8V supply voltage [10]. This demonstrates the interest of process/design co-optimization of strain-induced layout effects. For next UTBB-FDSOI nodes below 14nm, both the electrostatics and the carrier mobility must be improved. For the hole mobility, one may think about changing the crystalline orientation of the channel and using (110)-oriented substrates. However, in terms of electronic transport, the long channel carrier mobility is no longer the most relevant electrical parameter. One should pay a great attention to i) the strain compatibility and ii) the evolution of the apparent mobility with the gate length and width. Taking them into account, for pMOSFETs, SiGe channel + SiGeB source/drain + compressive contact etch stop layers in the (100) <110> direction is the best combination. For nMOSFETs, different technological solutions have been assessed, especially based on strain memorization techniques [6-7]. Strain-SOI substrates (sSOI) is another option, which brings enough performance boost to ensure a one-node scaling (+20-30% performance increase for nMOSFETs due to tensile strain, even for narrow active regions) [8]. Finally, the gate-last integration on planar FDSOI could be another strain booster because it leverages not only a low thermal budget for EOT and a threshold voltage optimization, but also a strain improvement during the final gate formation [9].

UTBB FDSOI: Evolution and opportunities

As today’s 28nm FDSOI (Fully Depleted Silicon On Insulator) technology is at the industrialization level, this paper aims to summarize the key advantages allowed by the thin BOX (Buried Oxide) of the FDSOI, through the technology evolution but also new opportunities, among logic applications and extending the possibilities offered by the platform. We will summarize how the advantages provided by the thin BOX have been first explored and developed, and how the back biasing techniques are the key to the outstanding performances provided by the FDSOI at low voltage. Then, as the FDSOI technology is also a solution to develop innovative platforms and applications, we will detail some opportunities. In particular, we will present monolithic 3D integration, ultra-low power devices for IoT (Internet of Things) and ultra-sensitive sensors.

Low-Leakage SRAM Wordline Drivers for the 28-nm UTBB FDSOI Technology

This brief deals with a new design of low-power SRAM wordline decoder in the 28-nm ultrathin body and buried oxide (UTBB) fully depleted silicon-on-insulator (FDSOI) technology. The proposed approach synergistically adopts the poly biasing technique in conjunction with single-well/flip-well configurations and body biasing to opportunely tune the threshold voltage of the devices in the standby and active mode. A tuning methodology is described to optimize the static energy consumption. Post-layout simulations, done at power supply voltages ranging between 1 V and 0.5 V, have shown that, in comparison with the state-of-the-art techniques based on the same UTBB FDSOI technology, the proposed design achieves a maximum leakage up to 85% lower without paying significant delay penalties.

Extensionless UTBB FDSOI Devices in Enhanced Dynamic Threshold Mode under Low Power Point of View

This work presents an analysis about the influence of the gate and source/drain underlap length (LUL) on UTBB FDSOI (UltraThin-Body-and-Buried-oxide Fully-Depleted-Silicon-On-Insulator) devices operating in conventional (VB = 0 V), dynamic threshold (DT, VB = VG), and the enhanced DT (eDT, VB = kVG) configurations, focusing on low power applications. It is shown that the underlap devices present a lower off-state current (IOFF at VG = 0 V), lower subthreshold swing (S), lower gate-induced drain leakage (GIDL), higher transconductance over drain current (gm/ID) ratio and higher intrinsic voltage gain (|AV|) due to their longer effective channel length in weak inversion and lower lateral electric field, while the eDT mode presents higher on-state current (ION) with the same IOFF, lower S, higher maximum transconductance (gmmax), lower threshold voltage (VT), higher gm/ID ratio and higher |AV| due to the dynamically reduced threshold voltage and stronger transversal electric field.