Use Of Field Programmable Gate Arrays Research Articles

A Real-Time Wavelet-Domain Video Denoising Implementation in FPGA

The use of field-programmable gate arrays (FPGAs) for digital signal processing (DSP) has increased with the introduction of dedicated multipliers, which allow the implementation of complex algorithms. This architecture is especially effective for data-intensive applications with extremes in data throughput. Recent studies prove that the FPGAs offer better solutions for real-time multiresolution video processing than any available processor, DSP or general-purpose. FPGA design of critically sampled discrete wavelet transforms has been thoroughly studied in literature over recent years. Much less research was done towards FPGA design of overcomplete wavelet transforms and advanced wavelet-domain video processing algorithms. This paper describes the parallel implementation of an advanced wavelet-domain noise filtering algorithm, which uses a nondecimated wavelet transform and spatially adaptive Bayesian wavelet shrinkage. The implemented arithmetic is decentralized and distributed over two FPGAs. The standard composite television video stream is digitalized and used as a source for real-time video sequences. The results demonstrate the effectiveness of the developed scheme for real-time video processing.

과학기술위성 2호 대용량 메모리 유닛 시험모델 설계 및 구현

본 논문에서는 과학기술위성 2호 대용량 메모리 유닛(Mass Memory Unit, MMU)의 시험모델(Engineering Model, EM)을 개발하고 기능 및 성능 시험한 결과를 제시하였다. 성능 구현에 필요한 로직들을 별도의 전용 칩들을 사용하지 않고 하나의 FPGA에 구현함으로써 대용량 메모리 유닛을 소형화, 경량화하고 저전력으로 사용할 수 있도록 하였다. 대용량 메모리는 2Gbits SDRAM 모듈을 사용하였으며 파일 시스템을 운용하여 지상국에서의 데이터 관리가 용이 하도록 하였다. 대용량 메모리에서 발생하는 SEU(Single Event Upset)를 극복하기 위해서 RS(207,187) 코드가 소프트웨어로 구현되어 있어서 187바이트당 10바이트의 에러를 복구할 수 있다. 또한 탑재체 데이터의 수신 성능을 검증하기 위해서 시뮬레이터를 제작 하였다. This paper describes the design and implementation of engineering model(EM) of Mass Memory Unit(MMU) for Science and Technology Satellite 2(STSAT-2) and the results of integration test. The use of Field-Programmable Gate Array(FPGA) instead of using private electric parts makes a miniaturization and lightweight of MMU possible. 2Gbits Synchronous Dynamic Random Access Memory(SDRAM) module for mass memory is used to store payload and satellite status data. Moreover, file system is applied to manage them easily in the ground station. RS(207,187) code improves the tolerance with respect to Single Event Upset(SEU) induced in SDRAM. The simulator is manufactured to verify receiving performance of payload data.

The Use of Field-Programmable Gate Arrays for the Hardware Acceleration of Design Automation Tasks

This paper investigates the possibility of using Field-Programmable Gate Arrays (Fpgas) as reconfigurable co-processors for workstations to produce moderate speedups for most tasks in the design process, resulting in a worthwhile overall design process speedup at low cost and allowing algorithm upgrades with no hardware modification. The use of Fpgas as hardware accelerators is reviewed and then achievable speedups are predicted for logic simulation and VLSI design rule checking tasks for various Fpga co-processor arrangements.

Report of the 1993 workshop on rapid prototyping of microelectronic systems for universities

Under sponsorship of the National Science Foundation, eleven participants from universities and industry and seven individuals from the NSF met during October 18-19, 1993, to assess the unique needs educators have for rapid prototyping of microelectronic systems and to suggest potential solutions for continuously improving the state-of-the-art in U.S. universities. The following vision statement was adopted: Educate students who can use the paradigm of design, simulate, design-for-test, build and test (as opposed to just design, build and test) to create microelectronic systems, not just integrated circuits tiCs), of sufficient quality that the global competitiveness of U.S. industry will be continued and enhanced. From this statement a number of findings and recommendations were made. Some of these include: (1) Student projects should be simulated thoroughly prior to submission to MOSIS for fabrication. (2) The use of Field-Programmable Gate Arrays (FPGAs) to support logic design and systems-oriented courses should be encouraged. (3) Fabrication services provided by MOSIS should be used largely for designs in which some portion has been performed manually. (4) NSF support for advanced classes should be broadened to include not only IC fabrication via MOSIS but also the acquistion of prototyping boards or multi-chip modules (MCMs) (5) Remote access via the Internet to expensive testers and prototyping systems should be made available. (6) MOSIS should add the following services: BiCMOS process, microelectro-mechanical post-processing, optoelectronic device fabrication and MCM prototyping. (7) A national clearinghouse should be supported to provide ready access by the educational community to existing and rapidly emerging resources that are presently dispersed. (8) Conferences, faculty enhancement short courses and newsletters should be supported to encourage widespread exchange of information.

A flat-aluminum based voltage-programmable link for field-programmable devices

A new metal-insulator-metal (MIM) structure has been developed for use in field-programmable gate arrays (FPGA's) as a voltage-programmable link (VPL). The present capacitor structure relies on aluminum metallization; hence, it should be amenable to immediate application. The addition of minute amounts of titanium or molybdenum has been found to suppress hillock formation. The insulator, prepared by means of plasma-enhanced chemical vapor deposition (PECVD), comprises a sandwich of a nearly stoichiometric silicon dioxide interposed between two like layers of silicon-rich silicon nitride. This MIM structure has displayed characteristics desirable for use in the emerging FPGA technology including high density, very low on-resistance, reduced capacitance, low programming voltage, and the potential for further scaling to the sub-micron regime. >

A novel metal-insulator-metal structure for field-programmable devices

A metal-insulator-metal (MIM) capacitor structure has been developed for use in field-programmable gate arrays (FPGAs) as a voltage-programmable link (VPL). The structure relies on a combination of a refractory metal and aluminum as the lower electrode, and either a similar combination or aluminum alone as the top electrode. The insulator is prepared by means of plasma-enhanced chemical vapor deposition (PECVD). It comprises a sandwich of nearly stoichiometric silicon dioxide interposed between two like layers of silicon-rich silicon nitride. The structure has displayed characteristics desirable for use in emerging FPGA technology, including high density, low on-resistance, reduced capacitance, and low programming voltage. >

HARDWARE IMPLEMENTATION OF FUZZY REPLACEMENT ALGORITHM FOR CACHE MEMORIES USING FIELD-PROGRAMMABLE GATE ARRAYS

A replacement algorithm based on fuzzy logic for set associative cache memories was proposed earlier. An effective hardware implementation for the fuzzy replacement algorithm will be presented here. The hardware is based on the use of field-programmable gate arrays (FPGAs). These devices combine the attractive features of programmable logic devices and gate arrays. The development of the schematic design, hardware simulation with gate delays, and subsequent configuration of the FPGA from the schematics are discussed. The timing diagram of the FPGA response is presented.

A novel double-metal structure for voltage-programmable links

A novel metal-insulator-metal (MIM) structure has been developed for use in field-programmable gate arrays (FPGAs) as a voltage-programmable link (VPL). The present structure relies on a combination of a refractory metal and aluminum as the lower electrode, and aluminum alone as the top electrode. The insulator, prepared by means of plasma-enhanced chemical vapor deposition, comprises a sandwich of nearly stoichiometric silicon dioxide interposed between two layers of silicon-rich silicon nitride. This MIM structure has displayed characteristics desirable for use in the emerging FPGA technology.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

GANGLION-a fast field-programmable gate array implementation of a connectionist classifier

71 The architecture, implementation, and application of GANGLION, a totally digital connectionist classifier, are described. This fully interconnected feedforward net with one hidden layer is capable of generating 4.48 billion interconnection/s. The architecture is realized on a single 9U VME card and is built entirely from off-the-shelf components. The very high throughput of 20 million decision/s is achieved by making efficient use of field-programmable gate arrays. Specifically, the authors take advantage of the reprogrammability of the devices to automatically generate new custom hardware for each application of the classifier. >