Use Of Field Programmable Gate Arrays Research Articles

Learning from the Past: Efficient High-level Synthesis Design Space Exploration for FPGAs

The quest to democratize the use of Field-Programmable Gate Arrays (FPGAs) has given High-Level Synthesis (HLS) the final push to be widely accepted with FPGA vendors strongly supporting this VLSI design methodology to expand the FPGA user base. HLS takes as input an untimed behavioral description and generates efficient RTL (Verilog or VHDL). One major advantage of HLS is that it allows us to generate a variety of different micro-architectures from the same behavioral description by simply specifying different combination of synthesis options. In particular, commercial HLS tools make extensive use of synthesize directives in the form pragmas. This strength is also a weakness as it forces HLS users to fully understand how these synthesis options work and how they interact to efficiently set them to get a hardware implementation with the desired characteristics. Luckily, this process can be automated. Unfortunately, the search space grows supra-linearly with the number of synthesis options. To address this, this work proposes an automatic synthesis option tuner dedicated for FPGAs. We have explored a larger number of behavioral descriptions targeting ASICs and FPGAs and found out that due to the internal structure of the FPGA a large number of synthesis options combinations never lead to a Pareto-optimal design and, hence, the search space can be drastically reduced. Moreover, we make use of large database of DSE results that we have generated since we started working in this field to further accelerate the exploration process. For this, we use a technique based on perceptual hashing that allows our proposed explorer to recognize similar program structures in the new description to be explored and match them with structures in our database. This allows us to directly retrieve the pragma settings that lead to Pareto-optimal configurations. Experimental results show that the search space can be accelerated substantially while leading to finding most of the Pareto-optimal designs.

Algorithmic Design of an FPGA-Based Calculator for Fast Evaluation of Tsunami Wave Danger

Events of a seismic nature followed by catastrophic floods caused by tsunami waves (the incidence of which has increased in recent decades) have an important impact on the populations of littoral regions. On the coast of Japan and Kamchatka, it takes nearly 20 min for tsunami waves to approach the nearest dry land after an offshore seismic event. This paper addresses an important question of fast simulation of tsunami wave propagation by mapping the algorithms in use in field-programmable gate arrays (FPGAs) with the help of high-level synthesis (HLS). Wave propagation is described by the shallow water system, and for numerical treatment the MacCormack scheme is used. The MacCormack algorithm is a direct difference scheme at a three-point stencil of a “cross” type; it happens to be appropriate for FPGA-based parallel implementation. A specialized calculator was designed. The developed software was tested for precision and performance. Numerical tests computing wave fronts show very good agreement with the available exact solutions (for two particular cases of the sea bed topography) and with the reference code. As the result, it takes just 17.06 s to simulate 1600 s (3200 time steps) of the wave propagation using a 3000 × 3200 computation grid with a VC709 board. The step length of the computational grid was chosen to display the simulation results in sufficient detail along the coastline. At the same time, the size of data arrays should provide their free placement in the memory of FPGA chips. The rather high performance achieved shows that tsunami danger could be correctly evaluated in a few minutes after seismic events.

Field-programmable gate arrays in a low power vision system

In recent years, field-programmable gate arrays have played a major role in developing low power electronic systems. End users usually prefer systems with high performance, reduced size, and low power consumption. These requirements create a challenging task for designers. Re-configuring technology allows the use of field-programmable gate arrays to be at the maximum level during runtime. This paper proposes the implementation of the Dynamic Partial Reconfiguration technique to switch during runtime between two edge detection algorithms (FASTX and Sobel) in a computer vision algorithm. Xilinx Ultrascale+ZCU106 has been used as the implementation target since it consumes approximately 4% less power during runtime. It was discovered that the dynamic switching between algorithms reduces the on-chip area utilization. Finally, through experimental results our proposed work has demonstrated the applicability of computer vision with low power consumption.

Power Distribution Attacks in Multitenant FPGAs

The increased use of field-programmable gate arrays (FPGAs) in the cloud and embedded computing environments has led to a number of potential security risks. The sizable amount of logic resources in these devices makes them amenable to sharing across multiple untrusted tenants. However, the co-location of multiple independent circuits presents the possibility of malicious fault injection into an unsuspecting circuit. In this article, the ability of one tenant's FPGA circuit to inject delay faults into another tenant's application located at points across the FPGA die via deliberate supply voltage modulation is investigated. To illustrate the risks involved, a Rivest-Shamir-Adleman (RSA) encryption key extraction attack is performed by introducing delay faults in hardware via voltage manipulations. This attack does not require modification to the encryption core nor require attack activation synchronized with specific encryption operations. Our work characterizes the magnitude of on-chip voltage changes and fault injections over time in relation to the on-chip location of the malicious circuit once an attack is initiated. Strategies to identify power manipulation using low-cost monitoring circuits that can locate the source of an attack are highlighted.

Performance and Implementation of Grid Connected Single Phase Photovoltaic System and FPGA-Design Based MPPT

Solar Photo Voltaic system are used for power generation by the process of photovoltaic effect. The solar power is varying continuously on a particular day due the variations in the temperature and irradiances. To overcome the power loss of PV system maximum power point tracking techniques are used to generate maximum solar power . Generally digital signal processors are used for implementing maximum power point tracking algorithms, but the performance is limited. The high degree of flexibility is achieved by the use of field-programmable gate arrays (FPGA) chips. The PV systems are used to provide stable and reliable power. The paper presents the single-phase implementation of the grid connected PV system and FPGS based P&O MPPT algorithm. The proposed system consists of P&O MPPT algorithm for maximum solar power extraction, bi-directional DC-DC converter for is used for controlling the battery. The solar power is used to serve the connected load and the excess power is used for serving grid utility. The single-phase inverter is used for DC-AC conversion. The Xilinx ISE is used for simulation of MPPT algorithm. The grid connected PV system is simulated using MATLAB/SIMULINK.

First Steps in Porting the LFRic Weather and Climate Model to the FPGAs of the EuroExa Architecture

In recent years, there has been renewed interest in the use of field-programmable gate arrays (FPGAs) for high-performance computing (HPC). In this paper, we explore the techniques required by traditional HPC programmers in porting HPC applications to FPGAs, using as an example the LFRic weather and climate model. We report on the first steps in porting LFRic to the FPGAs of the EuroExa architecture. We have used Vivado High-Level Syntheusywwi to implement a matrix-vector kernel from the LFRic code on a Xilinx UltraScale+ development board containing an XCZU9EG multiprocessor system-on-chip. We describe the porting of the code, discuss the optimization decisions, and report performance of 5.34 Gflop/s with double precision and 5.58 Gflop/s with single precision. We discuss sources of inefficiencies, comparisons with peak performance, comparisons with CPU and GPU performance (taking into account power and price), comparisons with published techniques, and comparisons with published performance, and we conclude with some comments on the prospects for future progress with FPGA acceleration of the weather forecast model. The realization of practical exascale-class high-performance computinems requires significant improvements in the energy efficiency of such systems and their components. This has generated interest in computer architectures which utilize accelerators alongside traditional CPUs. FPGAs offer huge potential as an accelerator which can deliver performance for scientific applications at high levels of energy efficiency. The EuroExa project is developing and building a high-performance architecture based upon ARM CPUs with FPGA acceleration targeting exascale-class performance within a realistic power budget.

Ultrasound Open Platforms for Next-Generation Imaging Technique Development.

Open platform (OP) ultrasound systems are aimed primarily at the research community. They have been at the forefront of the development of synthetic aperture, plane wave, shear wave elastography, and vector flow imaging. Such platforms are driven by a need for broad flexibility of parameters that are normally preset or fixed within clinical scanners. OP ultrasound scanners are defined to have three key features including customization of the transmit waveform, access to the prebeamformed receive data, and the ability to implement real-time imaging. In this paper, a formative discussion is given on the development of OPs from both the research community and the commercial sector. Both software- and hardware-based architectures are considered, and their specifications are compared in terms of resources and programmability. Software-based platforms capable of real-time beamforming generally make use of scalable graphics processing unit architectures, whereas a common feature of hardware-based platforms is the use of field-programmable gate array and digital signal processor devices to provide additional on-board processing capacity. OPs with extended number of channels (>256) are also discussed in relation to their role in supporting 3-D imaging technique development. With the increasing maturity of OP ultrasound scanners, the pace of advancement in ultrasound imaging algorithms is poised to be accelerated.

FPGA-Based Solutions for Analog Data Acquisition and Processing Integrated in Area Detector Using FlexRIO Technology

Analog data acquisition systems used for diagnostics and control of large physics experiments require high sampling rates and real-time processing functionalities. The use of field-programmable gate array (FPGA)-based devices allows efficient implementation of such solutions. Currently, large scientific facilities are using middleware platforms to simplify system integration. Experimental physics and industrial control system (EPICS) is one of the most popular middleware for this purpose. Moreover, heterogeneous hardware integration in these systems is a very complex task, and different approaches attempting to standardize this integration are under development and use. One of these approaches is areaDetector (AD), which involves an open source module for EPICS that is primarily used for image acquisition applications. AD simplifies the integration of heterogeneous image acquisition systems, providing a common interface between the hardware and EPICS. The AD community has already developed support for different cameras and communication protocols as well as different processing modules, including conversion to the most commonly used image formats. AD has also been used in some analog signal acquisition systems; for example, quadEM is typically used for a photodiode-based X-ray beam, but there are no implementations based on FPGA, such as FlexRIO technology. This paper presents the integration of acquisition and processing solution in a PXIe platform using the FlexRIO technology using a model that solves the acquisition and signal processing in an FPGA and a software layer implemented in C++ with the IRIO library (open source solution for RIO devices in the Linux environment).

Enhancing Security of FPGA-Based Embedded Systems with Combinational Logic Binding

With the increasing use of field-programmable gate arrays (FPGAs) in embedded systems and many embedded applications, the failure to protect FPGA-based embedded systems from cloning attacks has brought serious losses to system developers. This paper proposes a novel combinational logic binding technique to specially protect FPGA-based embedded systems from cloning attacks and provides a pay-per-device licensing model for the FPGA market. Security analysis shows that the proposed binding scheme is robust against various types of malicious attacks. Experimental evaluations demonstrate the low overhead of the proposed technique.

FPGAs versus GPUs in Data centers

This article presents position statements and a question-and-answer session by panelists at the Fourth Workshop on Computer Architecture Research Directions. The subject of the debate was the use of field-programmable gate arrays versus GPUs in datacenters.

VHDL Descriptions for the FPGA Implementation of PWL-Function-Based Multi-Scroll Chaotic Oscillators.

Nowadays, chaos generators are an attractive field for research and the challenge is their realization for the development of engineering applications. From more than three decades ago, chaotic oscillators have been designed using discrete electronic devices, very few with integrated circuit technology, and in this work we propose the use of field-programmable gate arrays (FPGAs) for fast prototyping. FPGA-based applications require that one be expert on programming with very-high-speed integrated circuits hardware description language (VHDL). In this manner, we detail the VHDL descriptions of chaos generators for fast prototyping from high-level programming using Python. The cases of study are three kinds of chaos generators based on piecewise-linear (PWL) functions that can be systematically augmented to generate even and odd number of scrolls. We introduce new algorithms for the VHDL description of PWL functions like saturated functions series, negative slopes and sawtooth. The generated VHDL-code is portable, reusable and open source to be synthesized in an FPGA. Finally, we show experimental results for observing 2, 10 and 30-scroll attractors.

FPGA-Based I&C Systems in Nuclear Plants

The FPGA (field programmable gate array) is a digital device widely used in various fields of industry. FPGAs can be used to perform functions that are safety critical and require high reliability, like in automobiles, aircraft control and assistance and mission-critical applications in the aerospace industry. With these merits, FPGAs are receiving increased attention worldwide for application in nuclear plant instrumentation and control (I&C) systems, mainly for Reactor Protection System (RPS).Reasons for this include the fact that conventional analog electronics technologies are become obsolete. I&C systems of new Reactors have been designed to adopt the digital equipment such as PLC (Programmable Logic Controller) and DCS (Distributed Control System). But microprocessors-based systems may not be simply qualified because of its complex characteristics. For example, microprocessor cores execute one instruction at a time, and an operating system is needed to manage the execution of programs. As a result, nuclear power plant operators and I&C suppliers may consider other non-computer-based digital technologies, such as devices that may be configured using HDL (Hardware Description Language).FPGAs, commonly referred to as HDL programmable devices (HPDs), can run without an operating system and the design architecture is inherently parallel. Despite the attractive features, the use of such programmable devices in safety critical systems for nuclear power plants is relatively new in many countries, and the regulatory approach to licensing such devices may not be clear.In this paper we aim to assess advantages and the limitations on FPGA-based solutions, considering the design guidelines and regulations on the use of FPGAs in Nuclear Plant I&C Systems. We will also examine some circuit design techniques in FPGA to help mitigate failures and provide resilience. The objective is to show how FPGA-based systems can provide cost-effective options for I&C systems in modernization projects, ensuring safe and reliable operation, meeting licensing requirements, such as separation, redundancy and diversity.

Sampling Effect Characterization of Digital SPWM of VSI in Time Domain

This paper characterizes the sampling effect in digital sinusoidal pulse width modulation (SPWM) of voltage source inverter (VSI). The time-domain analysis presented in this paper establishes the relation between the fundamental frequency, carrier frequency, and the sampling frequency at different modulation indices of the SPWM. The analysis investigates the effect of sampling frequency of the digital controller on the output of the VSI. It is shown that the low-frequency harmonic components appear in the frequency spectrum of the VSI output voltage due to sampling. As a result, the output current of digitally controlled VSI is stepped in nature. The double Fourier integral solution of the switched waveform for inner and outer integral limits has been used to derive the expression. The integral solution is obtained using Jacobi-Anger expansions. The generalized results developed in this paper are useful to investigate the sampling effect in high switching frequency DSPWM. The proposed sampling effect has been analyzed for SPWM of single-phase H-bridge inverter. The analytical results are verified using simulation and experimental results. The experimental results have been obtained with the use of field-programmable gate array (FPGA) as a digital controller.

Real-time simulation of dynamic vehicle models using a high-performance reconfigurable platform

With the increase in the complexity of models and lack of flexibility offered by the analog computers, coupled with the advancements in digital hardware, the simulation industry has subsequently moved to digital computers and increased usage of programming languages such as C, C++, and MATLAB. However, the reduced time-step required to simulate complex and fast systems imposes a tighter constraint on the time within which the computations have to be performed. The sequential execution of these computations fails to cope with the real-time constraints which further restrict the usefulness of Real-Time Simulation (RTS) in a Virtual Reality (VR) environment. In this paper, we present a methodology for the design and implementation of RTS algorithms, based on the use of Field-Programmable Gate Array (FPGA) technology. We apply our methodology to an 8th order steering valve subsystem of a vehicle with relatively low response time requirements and use the FPGA technology to improve the response time of this model. Our methodology utilizes traditional hardware/software co-design approaches to generate a heterogeneous architecture for an FPGA-based simulator by porting the computationally complex regions to hardware. The hardware design was optimized such that it efficiently utilizes the parallel nature of FPGAs and pipelines the independent operations. Further enhancement was made by building a hardware component library of custom accelerators for common non-linear functions. The library also stores the information about resource utilization, cycle count, and the relative error with different bit-width combinations for these components, which is further used to evaluate different partitioning approaches. In this paper, we illustrate the partitioning of a hardware-based simulator design across dual FPGAs, initiate RTS using a system input from a Hardware-in-the-Loop (HIL) framework, and use these simulation results from our FPGA-based platform to perform response analysis. The total simulation time, which includes the time required to receive the system input over a socket (without HIL), software initialization, hardware computation, and transfer of simulation results back over a socket, shows a speedup of 2 × as compared to a similar setup with no hardware acceleration. The correctness of the simulation output from the hardware has also been validated with the simulated results from the software-only design.

FPGA-based acceleration of MRI registration: an enabling technique for improving MRI-guided cardiac therapy

Background Quantification of edema and scar maps with cardiac MR images (cMRIs) enables effective Radiofrequency Ablation (RFA) of arrhythmias during the Electrophysiology (EP) procedure [1]. This demonstrates the paramount advantage over the EP catheterization under X-ray and ultrasound guidance. High-contrast and resolution cMRIs can be obtained preoperatively as a EP roadmap for surgical planning of RFA, whilst real-time MRI (rtMRI) can be used to guide catheterization and update the cMRI model [2] to provide intraoperative visualization of a 3D vascular map. A fast and efficient technique of non-rigid image co-registration is required. Although feature-based registration methods can be rapidly processed by computing sparse features, the outcome is sensitive to blurred images with artifacts that happens regularly in low-resolution rt-MRI, causing significant errors in feature detections. With the use of Field-programmable Gate Array (FPGA), we hypothesized that novel data structure and architecture of memory access can allow robust registration based on comparison of image intensity patterns, thus fulfilling the real-time requirements for clinical practice.

Reconfigurable Data Planes for Scalable Network Virtualization

Network virtualization presents a powerful approach to share physical network infrastructure among multiple virtual networks. Recent advances in network virtualization advocate the use of field-programmable gate arrays (FPGAs) as flexible high performance alternatives to conventional host virtualization techniques. However, the limited on-chip logic and memory resources in FPGAs severely restrict the scalability of the virtualization platform and necessitate the implementation of efficient forwarding structures in hardware. The research described in this manuscript explores the implementation of a scalable heterogeneous network virtualization platform that integrates virtual data planes implemented in FPGAs with software data planes created using host virtualization techniques. The system exploits data plane heterogeneity to cater to the dynamic service requirements of virtual networks by migrating networks between software and hardware data planes. We demonstrate data plane migration as an effective technique to limit the impact of traffic on unmodified data planes during FPGA reconfiguration. Our system implements forwarding tables in a shared fashion using inexpensive off-chip memories and supports both Internet Protocol (IP) and non-IP-based data planes. Experimental results show that FPGA-based data planes can offer two orders of magnitude better throughput than their software counterparts, and FPGA reconfiguration can facilitate data plane customization within 12 seconds. An integrated system that supports up to 15 virtual networks has been validated on the NetFPGA platform.

A scalable architecture for H.264/AVC variable block size motion estimation on FPGAs

In this paper, we investigate the use of Field-Programmable Gate Arrays (FPGAs) in the design of a highly scalable Variable Block Size Motion Estimation architecture for the H.264/AVC video encoding standard. The scalability of the architecture allows one to incorporate the system into low cost single FPGA solutions for low-resolution video encoding applications as well as into high performance multi-FPGA solutions targeting high-resolution applications. To overcome the performance gap between FPGAs and Application Specific Integrated Circuits, our design minimizes the increase in memory bandwidth as the design scales. The core computing unit of the architecture is implemented on FPGAs and its performance is reported. It is shown that the computing unit is able to achieve 58 frames per second (fps) performance for 640×480 resolution VGA video while incurring only 4.5% LUT and 6.3% DFF utilization on a Xilinx XC5VLX330 FPGA. With 8 computing units at 38% LUT and 55% DFF utilization, the architecture is able to achieve 50 fps performance for encoding full 1920×1088 progressive HDTV video.

An FPGA-Based Optical Transmitter Design Using Real-Time DSP for Advanced Signal Formats and Electronic Predistortion

Advances in the performance and flexibility of future optical networks will be brought about through the use of high-speed digital signal processing (DSP) for the generation of advanced optical signal formats and the compensation of transmission impairments. The use of field-programmable gate arrays (FPGAs) to implement experimental transceivers employing novel DSP techniques is attractive, as they are of low cost and are reprogrammable. In this paper, the design of a reprogrammable FPGA-based 10-Gb/s optical transmitter using real-time DSP is described and assessed through simulation. Using a single Xilinx Virtex-4 FPGA, digital filtering based on lookup tables with up to 12-bit addressing could be implemented. We also present, for the first time, a simulation technique using industry-standard digital design simulation tools (mentor graphics modelsim) in combination with a simulation of analog microwave components, optical transmission, and bit-error-rate estimation to assess the performance of the full transmission system. This simulation technique is used to demonstrate 10-Gb/s transmission over 550 km of standard single-mode fiber (SSMF) using electronic predistortion (EPD) and the generation of optical single sideband signals. A proof-of-principle experiment is described in which a single 10.7-Gb/s Mach-Zehnder modulator drive signal with 4-bit amplitude resolution and 1-sample/bit temporal resolution was generated. This was used as the input to Monte Carlo simulations to assess EPD transmission performance over SSMF links of up to 640 km.

Design-specific path delay testing in lookup-table-based FPGAs

Due to the increased use of field-programmable gate arrays (FPGAs) in production circuits with high reliability requirements, the design-specific testing of FPGAs has become an important topic for research. Path delay testing of FPGAs is especially important since path delay faults can render an otherwise fault-free FPGA unusable for a given design layout. This paper presents a new approach for FPGA path delay testing, which partitions target paths into subsets that are tested in the same test configuration. Each path is tested for all combinations of signal inversions along the path length. Each configuration consists of a sequence generator, response analyzer, and circuitry for controlling inversions along tested paths, all of which are formed from FPGA resources not currently under test. Two algorithms are presented for target-path partitioning to determine the number of required test configurations. The test circuitry associated with these methods is also described. The results of applying the methods indicate that our path-delay-testing approach requires seconds per design to cover all paths with delay within 10% of the critical path delay. The approach has been validated using Xilinx Virtex devices.

A Real-Time Wavelet-Domain Video Denoising Implementation in FPGA

The use of field-programmable gate arrays (FPGAs) for digital signal processing (DSP) has increased with the introduction of dedicated multipliers, which allow the implementation of complex algorit...