A scalable architecture for H.264/AVC variable block size motion estimation on FPGAs

Abstract

In this paper, we investigate the use of Field-Programmable Gate Arrays (FPGAs) in the design of a highly scalable Variable Block Size Motion Estimation architecture for the H.264/AVC video encoding standard. The scalability of the architecture allows one to incorporate the system into low cost single FPGA solutions for low-resolution video encoding applications as well as into high performance multi-FPGA solutions targeting high-resolution applications. To overcome the performance gap between FPGAs and Application Specific Integrated Circuits, our design minimizes the increase in memory bandwidth as the design scales. The core computing unit of the architecture is implemented on FPGAs and its performance is reported. It is shown that the computing unit is able to achieve 58 frames per second (fps) performance for 640×480 resolution VGA video while incurring only 4.5% LUT and 6.3% DFF utilization on a Xilinx XC5VLX330 FPGA. With 8 computing units at 38% LUT and 55% DFF utilization, the architecture is able to achieve 50 fps performance for encoding full 1920×1088 progressive HDTV video.