Abstract
By the arrival of latest video standards viz. MPEG-4 part 10 and H.264/H.26L, the usages of Advanced Video Coding (AVC) especially in the part of Variable Block Size (VBS) Motion Estimation (ME) are rising. A new architecture is developed for variable block size motion estimation using full search algorithm in this paper. There are two calculations carried out in this paper block size, which is variable, and another is the Sum of Absolute Differences (SAD), which are presented by recycling the outputs of reduced sub-block calculations. Mechanism that is incorporated by every processing element is shuffling mechanism. HDL verification is done through ModelSim simulator to verify the functionality. The design is implemented using TSMC 90nm CMOS technology. The frequency of the motion estimation block is 323.20 MHz, which can treat up to 41 Motion Vectors (MV).
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
