A SAD architecture for variable block size motion estimation in H.264 video coding

Abstract

In this paper, the high throughput hardware architecture is designed to calculate the Sum of Absolute Difference (SAD) based on the variable block size of the image. Even though the fixed block size motion estimation is simple with respect to the complexity of the variable block size motion estimation, variable block size estimation technique results in exquisite performance. Motion estimation is a crucial module/block which plays a major role in computing the efficiency of video coding. Because of variable block size in H.264, motion estimation becomes more complex and requires most efficient hardware for implementation in real-time video coding. The hardware implementation of SAD is done using Comparator and Carry skip adder. The comparator is used to implement the absolute difference unit, which is used to calculate the absolute difference values between each pixel of the current frame and the reference frame. Carry skip adder is used to add all the output values of the absolute difference unit. Carry skip adder improves the performance of the arithmetic operation. It does not wait for carrying to propagate which helps in increasing the speed of operation of adding. Comparator and Carry skip adder unit improves the performance of SAD calculation in terms of speed, area, and power. We had also proposed a control unit for H.264 video. This proposed control unit calculates the SAD output values according to block size given as input to control unit.