Use Of Dynamic Reconfiguration Research Articles

Efficient and Flexible Dynamic Reconfiguration for Multi Context Architectures

Dynamic reconfiguration is possible on both fine-grain and coarse-grain architectures. One of the used methodology used consists in the use of multi-context architectures. Unfortunately, the multiple contexts bring power and area overhead. This paper introduces the Dynamic Unifier and reConfigurable blocK (DUCK) concept, a new structure to perform efficiently dynamic reconfiguration on both custom designed fine-grain and coarse grain architectures. The DUCK allows to separate the configuration path and the configuration registers which facilitates simultaneous configuration and computing steps. The reconfiguration process is presented in detail, and synthesis results are given for different structures. Our solution is finally validated with the implementation of a WCDMA (Wideband Code Division Multiple Access) receiver on a multi-context embedded FPGA and on the dynamically reconfigurable processor DART. This implementation demonstrates the interest and the efficiency of the use of dynamic reconfiguration and the proposed flexible structure.

The laboratory tester of solar cells with dynamic reconfigutration of measuring system

An express meter of photovoltaic solar cells based on the programmable system on a chip PSoC5 and a personal computer is proposed. This tester is best suited for research on experimental samples of solar cells with non-standard dimensions and parameters, but can also be used as a standard tester for standard samples to control their characteristics with high precision. For the implementation a minimum of discrete elements — a PSoC5 chip, a transistor and a couple of resistors and diodes are required. And such devices as voltage supplies and a computer are available in each laboratory. The standard test conditions (irradiance 1 kW per sq.meter; spectral distribution AM 1.5; sample temperature 25oC) are conditions that obtainable in a laboratory by using a xenon single flash tube or by an incandescent lamp with filter to reduce the red part of spectra. Despite of the simplicity of the implementation the tester performs measurements of the basic parameters of solar cells (open-circuit voltage, short-circuit current, internal serial resistance and shunt resistance, maximum power, voltage and current at maximum power, efficiency, fill factor, short circuit current density) with high precision and charting current-voltage characteristic of solar cell during less than a second. All the parameters and the current-voltage characteristic are automatically saved to a file and can be examined later. Advantages of the tester are a low cost and highly flexible implementation of the measuring system that allows you to explore experimental samples of solar cells with different characteristics. This was implemented through the use of dynamic reconfiguration of system on a chip that adapts to the conditions of measurement. Depending on the photoelectric current, the algorithm, written in the memory of the programmable system on a chip, selects the appropriate configuration of the measuring system and adjusts the bit resolution (up to 20 bit) and type of the analog-to-digital converter, and gain of the built-in amplifier to provide a minimum time of measurement and maximum of accuracy at given conditions. This allows researchers to reduce the time for investigation of objects with unknown characteristics at a given measurement accuracy. In addition, a sufficient number of additional hardware resources of the programmable system on a chip (digital blocks for logic, timers, counters, analog blocks for operational amplifiers, a programmable gain amplifier, comparators, mixer sample and hold circuit, etc.) with the possibility of their easy configuration into the electronic circuit in the graphic mode of the PSoC Creator allows to researchers easily and quickly to fill up / adjust the electrical scheme to their needs without the need to change the circuit board of the device. The presence on the PSoC of the ARM Cortex-M3 32-bit CPU and the 24-bit fixed-point digital filter processor allows the researcher to supplement the measurement circuitry with digital signal processing, which is especially relevant for small-scale research samples with weak signals in the presence of noises.Ref. 10, fig. 7.

Dynamically Reconfigurable WSN Node Based on ISO/IEC/IEEE 21451 TEDS

Ubiquitous and plug-and-play are fundamental characteristics for the development of wireless sensor networks (WSNs). The ISO/IEC/IEEE 21451 family of standards has recently awakened its interest in this development, making easier the introduction of both characteristics in the design of wireless sensor nodes. Dynamic reconfigurability is also an exciting topic that is gathering interest for the development of embedded systems and smart sensor nodes in the last few years. The use of dynamic reconfiguration increases the scalability and heterogeneity capabilities of the sensor network. However, the ISO/IEC/IEEE 21451 standards do not handle dynamically reconfigurable nodes and previously proposed frameworks do not include this capability into novel wireless sensor nodes. In this paper, an ISO/IEC/IEEE 21451 transducer electronic data sheet (TEDS) architecture for the management of reconfigurable WSNs nodes is proposed. To test the node architecture and validate its capability, the proposed TEDS was implemented for an environmental sensor network.

Energy Efficiency Improvement by Dynamic Reconfiguration for Embedded Systems

SUMMARY This paper seeks to improve power-performance efficiency of embedded systems by the use of dynamic reconfiguration. Programmable logic devices (PLDs) have the competence to optimize the power consumption by the use of partial and/or dynamic reconfiguration. It is a non-exclusive approach, which can use other power-reduction techniques simultaneous, and thus it is applicable to a myriad of systems. The power-performance improvement by dynamic reconfiguration was evaluated through an augmented reality system that translates Japanese into English. It is a wearable and mobile system with a head-mounted display (HMD). In the system, the computing core detects a Japanese word from an input video frame and the translated term will be output to the HMD. It includes various image processing approaches such as pattern recognition and object tracking, and these functions run sequentially. The system does not need to prepare all functions simultaneously, which provides a function by reconfiguration only when it is needed. In other words, by dynamic reconfiguration, the spatiotemporal module-based pipeline can introduce the reduction of its circuit amount and power consumption compared to the naive approach. The approach achieved marked improvements; the computational speed was the same but the power consumption was reduced to around 1 .

A Self-Reconfigurable Platform for the Implementation of 2D Filterbanks with Real and Complex-Valued Inputs, Outputs, and Filter Coefficients

We introduce a dynamically reconfigurable 2D filterbank that supports both real and complex-valued inputs, outputs, and filter coefficients. This general purpose filterbank allows for the efficient implementation of 2D filterbanks based on separable 2D FIR filters that support all possible combinations of input and output signals. The system relies on the use of dynamic reconfiguration of real/complex one-dimensional filters to minimize the required hardware resources. The system is demonstrated using an equiripple and a Gabor filterbank and the results using both real and complex-valued input images. We summarize the performance of the system in terms of the required processing times, energy, and accuracy.

A reconfigurable, power-efficient adaptive Viterbi decoder

Error-correcting convolutional codes provide a proven mechanism to limit the effects of noise in digital data transmission. Although hardware implementations of decoding algorithms, such as the Viterbi algorithm, have shown good noise tolerance for error-correcting codes, these implementations require an exponential increase in very large scale integration area and power consumption to achieve increased decoding accuracy. To achieve reduced decoder power consumption, we have examined and implemented decoders based on the reduced-complexity adaptive Viterbi algorithm (AVA). Run-time dynamic reconfiguration is performed in response to varying communication channel-noise conditions to match minimized power consumption to required error-correction capabilities. Experimental calculations indicate that the use of dynamic reconfiguration leads to a 69% reduction in decoder power consumption over a nonreconfigurable field-programmable gate array implementation with no loss of decode accuracy.

A survey of design techniques for system-level dynamic power management

Dynamic power management (DPM) is a design methodology for dynamically reconfiguring systems to provide the requested services and performance levels with a minimum number of active components or a minimum load on such components. DPM encompasses a set of techniques that achieves energy-efficient computation by selectively turning off (or reducing the performance of) system components when they are idle (or partially unexploited). In this paper, we survey several approaches to system-level dynamic power management. We first describe how systems employ power-manageable components and how the use of dynamic reconfiguration can impact the overall power consumption. We then analyze DPM implementation issues in electronic systems, and we survey recent initiatives in standardizing the hardware/software interface to enable software-controlled power management of hardware components.