Upstream Tracker Research Articles

Development of a MAPS-based upstream tracker for the LHCb upgrade II

The LHCb Upstream Tracker is a silicon strip tracking detector that started operation in the Run 3 of the LHC. To meet the requirements imposed by high occupancy and data rate at the HL-LHC, a new Upstream Pixel (UP) tracker is proposed for LHCb Upgrade II based on CMOS pixel sensors. A preliminary detector layout is presented. The design of a sensor in a 55 nm high-voltage CMOS technology is introduced and further development is in process. Performance studies of UP with simulation are also ongoing.

Design, production, burn-in and tests of the hybrid circuits of the Upstream Tracker at the LHCb detector

We present a description of the design process, prototyping and production of the hybrid circuits for the front-end electronics of the Upstream Tracker at LHCb. The multilayer polyamide-based printed circuit boards, or hybrids, are designed to host the front-end ASICs. The ASICs require an optimized power delivery network from 0 to 120 MHz, with a maximum of 10−2 Ohms round-trip resistance, and 100 Ohms differential traces. Hybrids are required to have minimal radiation length, and to withstand the harsh environmental conditions of the data taking through intrinsic radiation hardness characteristics.

MAPS for the Upstream Tracker in LHCb Upgrade II

Upstream Tracker is a new tracking detector for LHCb Upgrade I to start operation in Run3 of LHC. In light of the plan of LHCb Upgrade II, simulation studies show that the current detector cannot operate due to the high occupancy and data rate. A first preliminary design is proposed to replace the Upstream Tracker with CMOS based detector, and available technology for future R&D are considered.

The SALT-Readout ASIC for Silicon Strip Sensors of Upstream Tracker in the Upgraded LHCb Experiment.

SALT, a new dedicated readout Application Specific Integrated Circuit (ASIC) for the Upstream Tracker, a new silicon detector in the Large Hadron Collider beauty (LHCb) experiment, has been designed and developed. It is a 128-channel chip using an innovative architecture comprising a low-power analogue front-end with fast pulse shaping and a 40 MSps 6-bit Analog-to-Digital Converter (ADC) in each channel, followed by a Digital Signal Processing (DSP) block performing pedestal and Mean Common Mode (MCM) subtraction and zero suppression. The prototypes of SALT were fabricated and tested, confirming the full chip functionality and fulfilling the specifications. A signal-to-noise ratio of about 20 is achieved for a silicon sensor with a 12 pF input capacitance. In this paper, the SALT architecture and measurements of the chip performance are presented.

Simulation and Optimization Studies of the LHCb Beetle Readout ASIC and Machine Learning Approach for Pulse Shape Reconstruction.

The optimization of the Beetle readout ASIC and the performance of the software for the signal processing based on machine learning methods are presented. The Beetle readout chip was developed for the LHCb (Large Hadron Collider beauty) tracking detectors and was used in the VELO (Vertex Locator) during Run 1 and 2 of LHC data taking. The VELO, surrounding the LHC beam crossing region, was a leading part of the LHCb tracking system. The Beetle chip was used to read out the signal from silicon microstrips, integrating and amplifying it. The studies presented in this paper cover the optimization of its electronic configuration to achieve the lower power consumption footprint and the lower operational temperature of the sensors, while maintaining a good condition of the analogue response of the whole chip. The studies have shown that optimizing the operational temperature is possible and can be beneficial when the detector is highly irradiated. Even a single degree drop in silicon temperature can result in a significant reduction in the leakage current. Similar studies are being performed for the future silicon tracker, the Upstream Tracker (UT), which will start operating at LHC in 2021. It is expected that the inner part of the UT detector will suffer radiation damage similar to the most irradiated VELO sensors in Run 2. In the course of analysis we also developed a general approach for the pulse shape reconstruction using an ANN approach. This technique can be reused in case of any type of front-end readout chip.

Advancements and plans for the LHC upgrade detector thermal management with CO2 evaporative cooling

Following its pioneering application in the present LHCb Velo detector, CO 2 evaporative cooling has become the consolidated technology for the thermal management of low-temperature operated silicon detectors at LHC. ATLAS Insertable B-Layer and CMS Phase I Pixel are successfully operating with such cooling system since a few years and LHCb has selected the same technology for the new Upstream Tracker and the upgraded Velo, both to be installed during LS2. The design of the ATLAS and CMS upgrade silicon detectors is well advanced, and both experiments heavily rely on CO 2 evaporative cooling. In order to cope with the new detector requirements, several studies are on-going, in particular on the scaling of the cooling plants, their integration in the existing space and infrastructure, the low temperature operation . A demonstrator cooling system, the “Demo”, is presently in the design phase at CERN. This paper discusses the challenges of the CO 2 systems for the phase 2 upgrade of the LHC experiments, the design of the “Demo” cooling system and the integration and operational issues under study, presenting a time-line for the CO 2 system development from now up to operation.

8-channel prototype of SALT readout ASIC for Upstream Tracker in the upgraded LHCb experiment

SALT is a new 128-channel readout ASIC for silicon strip detectors in the upgraded Upstream Tracker of the LHCb experiment. It will extract and digitise analogue signals from the sensor, perform digital processing and transmit serial output data. SALT is designed in CMOS 130 nm process and uses a novel architecture comprising of an analogue front-end and an ultra-low power (<0.5 mW) fast (40 MSps) sampling 6-bit ADC in each channel. An 8-channel prototype (SALT8), comprising all important functionalities was designed, fabricated and tested. A full 128-channel version was also submitted. The design and test results of the SALT8 prototype are presented showing its full functionality.

The upstream tracker for the LHCb upgrade

The LHCb collaboration is planning a comprehensive upgrade of the experiment for the long shutdown of the LHC in 2019/20. As part of this upgrade, the tracking station in front of the LHCb dipole magnet will be replaced by a new planar four-layer silicon micro-strip detector with 40MHz readout and silicon sensors with finer granularity and improved radiation hardness. Key design aspects of this new Upstream Tracker are described and a brief overview of the status of the project is given.

SALT, a dedicated readout chip for high precision tracking silicon strip detectors at the LHCb Upgrade

The Upstream Tracker (UT) silicon strip detector, one of the central parts of the tracker system of the modernised LHCb experiment, will use a new 128-channel readout ASIC called SALT. It will extract and digitise analogue signals from the UT sensors, perform digital signal processing and transmit a serial output data. The SALT is being designed in CMOS 130 nm process and uses a novel architecture comprising of analog front-end and fast (40 MSps) ultra-low power (<0.5 mW) 6-bit ADC in each channel. The prototype ASICs of important functional blocks, like analogue front-end, 6-bit SAR ADC, PLL, and DLL, were designed, fabricated and tested. A prototype of an 8-channel version of the SALT chip, comprising all important functionalities was also designed and fabricated. The architecture and design of the SALT, together with the selected preliminary tests results, are presented.

Tracking system of the upgraded LHCb

The upgrade of the LHCb experiment will run at an instantaneous luminosity up to 2×1033cm−2s−1 with a fully software based trigger, allowing us to read out the detector at a rate of 40MHz. For this purpose, the full tracking system will be newly developed: the vertex locator (VELO) will be replaced by a pixel-based detector providing an excellent track reconstruction with an efficiency of above 99%. Upstream of the magnet, a silicon micro-strip detector with a high granularity and an improved acceptance, called the Upstream Tracker (UT) will be placed. The tracking system downstream of the magnet will be replaced by the Scintillating Fibre tracker (SciFi), which will consist of 12 layers using 2.5m long scintillating fibres read out by silicon photo-multipliers.

Testbeam studies of pre-prototype silicon strip sensors for the LHCb UT upgrade project

The LHCb experiment is preparing for a major upgrade in 2018–2019. One of the key components in the upgrade is a new silicon tracker situated upstream of the analysis magnet of the experiment. The Upstream Tracker (UT) will consist of four planes of silicon strip detectors, with each plane covering an area of about 2m2. An important consideration of these detectors is their performance after they have been exposed to a large radiation dose. In this paper we present test beam results of pre-prototype n-in-p and p-in-n sensors that have been irradiated with fluences up to 4.0×1014neq/cm2.

CO2 evaporative cooling: The future for tracking detector thermal management

In the last few years, CO2 evaporative cooling has been one of the favourite technologies chosen for the thermal management of tracking detectors at LHC. ATLAS Insertable B-Layer and CMS Pixel phase 1 upgrade have adopted it and their systems are now operational or under commissioning. The CERN PH-DT team is now merging the lessons learnt on these two systems in order to prepare the design and construction of the cooling systems for the new Upstream Tracker and the Velo upgrade in LHCb, due by 2018. Meanwhile, the preliminary design of the ATLAS and CMS full tracker upgrades is started, and both concepts heavily rely on CO2 evaporative cooling. This paper highlights the performances of the systems now in operation and the challenges to overcome in order to scale them up to the requirements of the future generations of trackers. In particular, it focuses on the conceptual design of a new cooling system suited for the large phase 2 upgrade programmes, which will be validated with the construction of a common prototype in the next years.

Simulation of Upstream Tracker Detector Response for Modernised LHCb Experiment

LHCb experiment operates a forward spectrometer that collects proton‐ proton collision data at the Large Hadron Collider at CERN. During the so-called Long Shutdown 2 period in years 2018‐2019, LHCb detector will undergo a major modernisation. A vital part of this upgrade process is building a silicon micro-strip tracking detector — Upstream Tracker (UT) — that will be placed before the bending magnet. The UT will play a critical role in the upgraded trigger system. This paper contains a general discussion of the UT detector and presents description of a silicon response simulation platform that is being currently designed by the AGH UST LHCb group.

Emulation and Calibration of the SALT Read-out Chip for the Upstream Tracker for Modernised LHCb Detector

The LHCb is one of the four major experiments currently operating at CERN. The main reason for constructing the LHCb forward spectrometer was a precise measurement of the CP violation in heavy quarks section as well as search for a New Physics. To obtain interesting results, the LHCb is mainly focused on study of B meson decays. Unfortunately, due to the present data acquisition architecture, the LHCb experiment is statistically limited for collecting such events. This fact led the LHCb Collaboration to decide to perform far-reaching upgrade. Key part of this upgrade will be replacement of the TT detector. To perform this action, it was requited to design new tracking detector with entirely new front-end electronics. This detector will be called the Upstream Tracker (UT) and the read-out chip — SALT. This note presents an overall discussion on SALT chip. In particular, the emulation process of the SALT data preformed via the software written by the author.

The MICE spectrometers for the measurement of muon beam emittance

Tracking detectors based on 350‐μm scintillating fibers have been developed to measure muon-beam emittance at the Muon Ionization Cooling Experiment (MICE), the goal of which is to demonstrate ionization cooling by constructing and testing part of a cooling channel designed for a Neutrino Factory. The upstream and downstream trackers were assembled at the Rutherford Appleton Laboratory (RAL) in 2008 and 2009. The mechanical design and construction (including quality assurance) procedures used for the trackers are described in this paper. Results from the cosmic-ray test performed for the upstream tracker at RAL in 2008 are also presented.