Event Upset Research Articles

Theoretical and Experimental Study of Complementary Metal Oxide Semiconductor Inverters under High-Power Microwave Interferences

In this article, we report a study of the upset effects on complementary metal oxide semiconductor inverters under high-power microwave interferences. By means of SPICE simulations as well as experimental measurements, the output logic voltage waveforms of inverters were investigated through radio frequency pulse injection. A special radio frequency injection test setup was designed. The power level of the radio frequency pulses being directly injected into the inverters can be as high as 45 dBm, and their frequency ranged from 800 MHz to 4 GHz. The experimental results agreed well with the theoretical simulations, such as the variation rules of the output voltages as well as some transient rising time values. Both the theoretical and experimental results indicate that the SPICE models can be used to evaluate the effects of intensive electromagnetic interference on the digital circuits. Particularly, the variation of the susceptibility of complementary metal oxide semiconductor inverters versus the frequency follows the function f2, and a strong frequency suppression effect is also observed at radio frequencies higher than C band. Finally, the threshold level of logic failure can be significantly affected by the input logic state of the inverters.

Noninvasive Fault Classification, Robustness and Recovery Time Measurement in Microprocessor-Type Architectures Subjected to Radiation-Induced Errors

In critical digital designs such as aerospace or safety equipment, radiation-induced upset events (single-event effects or SEEs) can produce adverse effects, and therefore, the ability to compare the sensitivity of various proposed solutions is desirable. As custom-hardened microprocessor solutions can be very costly, the reliability of various commercial off-the-shelf (COTS) processors can be evaluated to see if there is a commercially available microprocessor or microprocessor-type intellectual property (IP) with adequate robustness for the specific application. Most existing approaches for the measurement of this robustness of the microprocessor involve diverting the program flow and timing to introduce the bit flips via interrupts and embedded handlers added to the application program. In this paper, a tool based on an emulation platform using Xilinx field programmable gate arrays (FPGAs) is described, which provides an environment and methodology for the evaluation of the sensitivity of microprocessor architectures, using dynamic runtime fault injection. A case study is presented, where the robustness of MicroBlaze and Leon3 microprocessors executing a simple signal processing task written in C language is evaluated and compared. A hardened version of the program, where the key variables are protected, has also been tested, and its contributions to system robustness have also been evaluated. In addition, this paper presents a further improvement in the developed tool that allows not only the measurement of microprocessor robustness but, in addition, the study and classification of single-event upset (SEU) effects and the exact measurement of the recovery time (the time that the microprocessor takes to self repair and recover the fault-free state). The measurement of this recovery time is important for real-time critical applications, where criticality depends on both data correctness and timing. To demonstrate the proposed improvements, a new software program that implements two different software hardening techniques (one for Data and another for Control Flow) has been made, and a study of the recovery times in some significant fault-injection cases has been performed over the Leon3 processor.

Three-dimensional numerial simulation of single event upset effects in static random access memory

Three-Dimensional model of static random access memory （SRAM） six-transistor cell is generated by three dimensional process simulator FLOOPS, and device simulator DESSIS is used to simulate the single-event upset effect in SRAM. Single-event upset and charge collecting maps are calculated directly from 3-D simulations. Single event upset maps and cross-section curves obtained from numerial simulation show excellent agreement with broad beam cross section curves and micro-beam upset images for 2 kbit hardened SRAM. It indicates that the three-dimensional model could be used to research the single event upsets in SRAM.

Study on the dose rate upset effect of partially depleted silicon-on-insulator static random access memory

This paper implements the study on the Dose Rate Upset effect of PDSOI SRAM (Partially Depleted Silicon-On-Insulator Static Random Access Memory) with the Qiangguang-I accelerator in Northwest Institute of Nuclear Technology. The SRAM (Static Random Access Memory) chips are developed by the Institute of Microelectronics of Chinese Academy of Sciences. It uses the full address test mode to determine the upset mechanisms. A specified address test is taken in the same time. The test results indicate that the upset threshold of the PDSOI SRAM is about 1×108 Gy(Si)/s. However, there are a few bits upset when the dose rate reaches up to 1.58 × 109 Gy(Si)/s. The SRAM circuit can still work after the high level γ ray pulse. Finally, the upset mechanism is determined to be the rail span collapse by comparing the critical charge with the collected charge after γ ray pulse. The physical locations of upset cells are plotted in the layout of the SRAM to investigate the layout defect. Then, some layout optimizations are made to improve the dose rate hardened performance of the PDSOI SRAM.

Soft-error resilience of the IBM POWER6 processor input/output subsystem

The soft-error resilience of the IBM POWER6™ processor I/O (input/output) subsystem was measured using proton beam irradiation to accelerate the effect of single-event upsets. Test programs exercised each of the adapters on the chip. Error rates were measured for various cases ranging from idle to high I/O bandwidth and utilization. The POWER6 processor and I/O hub subsystem work together to maintain resiliency even under strenuous irradiation conditions.

Soft-error resilience of the IBM POWER6 processor

The error detection and correction capability of the IBM POWER6™ processor enables high tolerance to single-event upsets. The soft-error resilience was tested with proton beam- and neutron beam-induced fault injection. Additionally, statistical fault injection was performed on a hardware-emulated POWER6 processor simulation model. The error resiliency is described in terms of the proportion of latch upset events that result in vanished errors, corrected errors, checkstops, and incorrect architected states.

Transient Radiation Response of Single- and Multiple-Gate FD SOI Transistors

The transient radiation response of single- and multiple-gate fully depleted silicon-on-insulator (FD SOI) transistors is investigated with heavy ion and pulsed laser experiments. Very fast transients are shown on single-gate devices while non-planar Omega-gate transistors exhibit longer transient pulses. The current process of multi-gate devices, which includes long resistive access to source and drain electrodes, is shown to be responsible for these longer pulses, they are not an intrinsic characteristic of multi-gate devices. The charge collection mechanisms are discussed with 3-D device simulations as a function of device architecture and design. Mixed-mode simulations are used to present trends on the sensitivity to single event upset and single event transient of elementary cells based on a 50 nm FD SOI technology.

A Generalized SiGe HBT Single-Event Effects Model for On-Orbit Event Rate Calculations

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> This work draws on experimental and simulation results to derive a generalized SEU response model for bulk SiGe HBTs. The model was validated using published heavy ion and new proton data gathered from high-speed HBT digital logic integrated circuits fabricated in the IBM 5AM SiGe BiCMOS process. Calibrating to heavy ion data was sufficient to reproduce the proton data without further adjustment. The validated model is used to calculate upset event rates for low-earth and geosynchronous orbits under typical conditions. </para>

Error Correction On-Demand: A Low Power Register Transfer Level Concurrent Error Correction Technique

Errors introduced by radiation-induced single event upset and single event latchup in very deep submicron (VDSM) ICs necessitate concurrent error detection (CED) and correction. Power consumed by circuits used for detecting and correcting errors becomes an extra burden on the tight power budget of VDSM ICs. The triple-modular redundancy-based fault tolerance technique, which is traditionally used for error detection and correction, incurs over 200 percent power overhead. In this paper, we propose register-transfer level low-power on-demand error correction techniques. Proposed techniques implement an original computation and a recomputation in datapath and compare the results from two computations to monitor the health of circuit. A mismatch in results indicates faulty computation and a second recomputation is triggered to rectify the error. The proposed techniques can detect and correct SEU induced transient errors and detect SEL induced permanent errors with as little as 12 percent power overhead

Single-Event Upset and Scaling Trends in New Generation of the Commercial SOI PowerPC Microprocessors

Single-event upset effects from heavy ions are measured for Motorola silicon-on-insulator (SOI) microprocessor with 90 nm feature sizes. The results are compared with previous results for SOI microprocessors with feature sizes of 130 and 180 nm. The cross section of the 90 nm SOI processors is smaller than results for 130 and 180 nm counterparts, but the threshold is about the same. The scaling of the cross section with reduction of feature size and core voltage for SOI microprocessors is discussed

Icing Encounter Flight Simulator

The Icing Encounter Flight Simulator is one part of the Smart Icing Systems project at the University of Illinois at Urbana-Champaign. From the Smart Icing Systems project, an ice management system was designed that would sense and characterize ice, notify the pilot, and if necessary take measures to ensure the safety of the aircraft. The icing simulator was used as a platform to integrate and test different components of the Smart Icing System. To create an Icing Encounter Flight Simulator, functionality and Smart Icing System components were added to the FlightGear flight simulator. Functionality added to FlightGear include a reconfigurable aircraft model and an icing model, and Smart Icing System components added include an envelope protection system and a glass cockpit enhanced with ice management system features. To ensure a real-time simulation, computationally intensive processes were distributed over several desktop computers linked together through a local network. In order to demonstrate the effectiveness of the Smart Icing System components, two fictional but historically motivated icing scenarios were developed and tested with a simulated DeHavilland DHC-6 Twin Otter, specifically, a tailplane stall event during a steep descent and a roll upset event during an emergency approach. Language: en

Investigation of multi-bit upsets in a 150 nm technology SRAM device

Multi-bit upset (MBU) events collected from accelerated soft error rate (SER) measurements performed with a quasi-monoenergetic neutron beam were analyzed with a threefold purpose. The first goal was to qualitatively assess the applicability and effectiveness of single-bit Error Detection And Correction algorithms and circuits (EDAC). The second goal was to investigate the relationship with the memory core P-well tapping scheme. And the third goal was to identify "preferred" MBU shapes. The results showed that the memory architecture is critical in affecting the single-bit EDAC effectiveness. Also, it was put in evidence that the tapping scheme is very effective in reducing the MBU rate. And finally it was noted that the predominant MBU shape is strongly influenced by the vertical and horizontal distance of the active nodes of the memory cells.

Single-event upset in highly scaled commercial silicon-on-insulator PowerPC microprocessors

Single-event upset effects from heavy ions are measured for Motorola and IBM silicon-on-insulator (SOI) microprocessors with different feature sizes and core voltages. The results are compared with results for similar devices with bulk substrates. The cross sections of the SOI processors are lower than their bulk counterparts, but the threshold is about the same, even though the charge collections depth is more than an order of magnitude smaller in the SOI devices. The scaling of the cross section with reduction of feature size and core voltage dependence for SOI microprocessors is discussed.

High-energy heavy ion testing of VLSI devices for single event upsets and latch up

Several very large scale integrated (VLSI) devices which are not available in radiation hardened version are still required to be used in spacecraft systems. Thus these components need to be tested for highenergy heavy ion irradiation to find out their tolerance and suitability in specific space applications. This paper describes the high-energy heavy ion radiation testing of VLSI devices for single event upset (SEU) and single event latch up (SEL). The experimental set up employed to produce low flux of heavy ions viz. silicon (Si), and silver (Ag), for studying single event effects (SEE) is briefly described. The heavy ion testing of a few VLSI devices is performed in the general purpose scattering chamber of the Pelletron facility, available at Nuclear Science Centre, New Delhi. The test results with respect to SEU and SEL are discussed.

The impact of floc size on respiration inhibition by soluble toxicants—a comparative investigation

Activated sludge facilities are susceptible to upset by shock loads of toxic compounds. We hypothesized that floc size plays an important role in determining the sensitivity of mixed liquor to shock by cadmium and 2,4-dinitrophenol (DNP). To test this hypothesis, heterotrophic respiration inhibition experiments were conducted using mixed liquor from a pilot-scale membrane bioreactor (MBR) and full-scale activated sludge (FSAS) facility with gravity settling secondary clarifiers that were operated under similar process conditions. MBR mixed liquor flocs were both 41% smaller and 2 and 1.25 times more sensitive to equivalent soluble cadmium and DNP concentrations, respectively, compared to FSAS mixed liquor flocs. Similarly, FSAS mixed liquor that had been sheared (resulting in a smaller average floc diameter) was 1.5 times more sensitive to soluble cadmium than non-sheared FSAS mixed liquor. These results suggest that activated sludge process conditions that create smaller floc particles, such as the use of membranes for liquid–solid separation, are more susceptible to upset events caused by shock loads of cadmium and DNP. The particle size distribution (PSD) and average floc diameter of a mixed liquor suspension should be measured and reported when stating the inhibition concentration of a specific toxicant.

Edge triggered pulse latch design with delayed latching edge for radiation hardened application

We describe a novel edge triggered pulse latch design with delayed latching edge. Combined with dual interlocked cell (DICE) slave latch stage, the presented design is radiation hardened to both static single event upset (SEU) and dynamic single event transient (SET) on its internal sensitive nodes. Delayed latching edge design enables a new block level radiation hardening circuit design approach to trade timing resources in nontiming critical paths with the radiation hardness.

Ion and electron track-structure and its effects in silicon: model and calculations

The dielectric-function-theory was used for systematic calculations of the inelastic interaction-characteristics of electrons and protons with different energies in silicon. An extended comparison of the calculated data with experiment and with the results of other models show that these data can serve as an accurate database for Monte Carlo simulations and other kinds of charged particle transport calculations. The new database was used to calculate the spatial distributions of: (i) the deposited energy by δ-electrons which are ejected by protons, (ii) the distances (from the ion trace) of holes and stopped electrons created in the ionization process and (iii) the separation between holes and electrons. These distributions have been used for the calculation of track-effect-parameters like the restricted LET and the mean prompt (transient) electrical field potentials. In addition to these “meanvalue” characteristics, we calculated the straggling of the ion energy-deposition, which is an important parameter in characterizing the process of single event upset. Similar data were obtained for electrons with energies up to 10keV. The calculated results are presented in a form which is suitable for various applications, like: microdosimetry, upset events in microelectronics, dose equivalence and others.

Comparison of Xilinx Virtex-II FPGA SEE sensitivities to protons and heavy ions

A comparison of heavy-ion and proton-induced single event effect sensitivities has been made using the Xilinx Virtex-II field programmable gate array (FPGA). Recently fabricated test samples are selected for observations of single event upset and single event functional interrupt. A complex relationship appears to exist between the heavy ion and proton sensitivities due to effects such as multiple-bit upsets and elastic nuclear scattering.

SEU mitigation for half-latches in Xilinx Virtex FPGAs

The performance, in-system reprogrammability, flexibility, and reduced costs of SRAM-based field programmable gate arrays (FPGAs) make them very interesting for high-speed on-orbit data processing, but the current generation of radiation-tolerant SRAM-based FPGAs are based on commercial-off-the-shelf technologies and, consequently, are susceptible to single-event upset effects. In this paper, we discuss in detail the consequences of radiation-induced single-event upsets (SEUs) in the state of half-latch structures found in Xilinx Virtex FPGAs and describe methods for mitigating the effects of half-latch SEUs. One mitigation method's effectiveness is then illustrated through experimental data gathered through proton accelerator testing at Crocker Nuclear Laboratory, University of California-Davis. For the specific design and mitigation methodology tested, the mitigated design demonstrated more than an order of magnitude improvement in reliability over the unmitigated version of the design in regards to average proton fluence until circuit failure.

Single-event upset in evolving commercial silicon-on-insulator microprocessor technologies

Single-event upset effects from heavy ions are measured for Motorola and IBM silicon-on-insulator (SOI) microprocessors with different feature sizes and core voltages. Multiple-bit upsets in registers and D-cache were measured and compared with single-bit upsets. Also, the scaling of the cross section with reduction of feature size for SOI microprocessors is discussed.