Unspecified Bits Research Articles

LFSR Reseeding-Oriented Low-Power Test-Compression Architecture for Scan Designs

Massive test data volume and excessive test power consumption have become two strict challenges for very large scale integrated circuit testing. In BIST architecture, the unspecified bits are randomly filled by LFSR reseeding-based test compression scheme, which produces enormous switching activities during circuit testing, thereby causing high test power consumption for scan design. To solve the above thorny problem, LFSR reseeding-oriented low-power test-compression architecture is developed, and an optimized encoding algorithm is involved in conjunction with any LFSR-reseeding scheme to effectively reduce test storage and power consumption, it includes test cube-based block processing, dividing into hold partition sets and updating hold partition sets. The main contributions is to decrease logic transitions in scan chains and reduce specified bit in test cubes generated via LFSR reseeding. Experimental results demonstrate that the proposed scheme achieves a high test compression efficiency than the existing methods while significantly reduces test power consumption with acceptable area overhead for most Benchmark circuits.

Test Data Compression with Alternating Equal-Run-Length Coding

This paper presents a new X-filling algorithm for test power reduction and a novel encoding technique for test data compression in scan-based VLSI testing. The proposed encoding technique focuses on replacing redundant runs of the equal-run-length vector with a shorter codeword. The effectiveness of this compression method depends on a number of repeated runs occur in the fully specified test set. In order to maximize the repeated runs with equal run length, the unspecified bits in the test cubes are filled with the proposed technique called alternating equal-run-length (AERL) filling. The resultant test data are compressed using the proposed alternating equal-run-length coding to reduce the test data volume. Efficient decompression architecture is also presented to decode the original data with lesser area overhead and power. Experimental results obtained from larger ISCAS'89 benchmark circuits show the efficiency of the proposed work. The AERL achieves up to 82.05 % of compression ratio as well as up to 39.81% and 93.20 % of peak and average-power transitions in scan-in mode during IC testing.

Two-stage low power test data compression for digital VLSI circuits

In this paper, we present a hybrid X-filling and two-stage test data compression (TS-TDC) techniques for digital VLSI circuits to reduce the test power and test data volume respectively. The proposed hybrid X-filling combines adjacent filling and modified 4m filling technique to reduce the switching activities of the scan cells. It divides the unspecified bits present in the test cubes by multiples of 4 to increase the correlation between the consecutive test patterns which in turn provides better run length for test data reduction. The filled test cubes are encoded with two stage test data compression in order to reduce test data volume. In the first stage, the completely specified test sets are encoded using Alternative Statistical Run Length (ASRL) coding to enhance the test data compression. The compressed ASRL test set is encoded further using Run Length based Huffman Coding (RLHC) since ASRL codewords contain the maximum run length of oneâ;;s. Experimental results show that the proposed hybrid filling provides the scan-in average and peak-power transition reduction of 88% and 29% respectively against original test sets. The two-stage test data compression scheme achieves a maximum of 86% and an average of 76% compression ratio for ISCAS’89 benchmark circuits.

FPGA IMPLEMENTATION OF RUN LENGTH ENCODING WITH NEW FORMULATED CODEWORD GENERATOR

There are two major impacts in today industry while testing larger integrated circuits like large test data volume and high test power. In our proposed scheme target both two issues for achieving two aforementioned goals in full scan sequential circuits. Shift power is reduced by one of the adjacent filling. During testing we are filling the unspecified bits in the test pattern with either 0’s or 1’s depend on nearest specified bit from left side. After filling the don’t care bits test data can be compressed by shifted alternate frequency directed run length encoding. A new formulated codeword generator is introduced and it generates infinite number of codeword for large size input test pattern. Using this codeword generator test data volume can be effectively compressed. The experimental results on ISCAS’89 benchmark circuit shows our scheme provides better efficiency as well as significant reduction in test power.

Enhancement of test data compression with multistage encoding

In this paper, we present two multistage compression techniques to reduce the test data volume in scan test applications. We have proposed two encoding schemes namely alternating frequency-directed equal-run-length (AFDER) coding and run-length based Huffman coding (RLHC). These encoding schemes together with the nine-coded compression technique enhance the test data compression ratio. In the first stage, the pre-generated test cubes with unspecified bits are encoded using the nine-coded compression scheme. Later, the proposed encoding schemes exploit the properties of compressed data to enhance the test data compression. This multistage compression is effective especially when the percentage of do not cares in a test set is very high. We also present the simple decoder architecture to decode the original data. The experimental results obtained from ISCAS'89 benchmark circuits confirm the average compression ratio of 74.2% and 77.5% with the proposed 9C-AFDER and 9C-RLHC schemes respectively.

Low-power selective pattern compression for scan-based test applications

The ever-increasing test data volume and test power consumption are the two major issues in testing of digital integrated circuits. This paper presents an efficient technique to reduce test data volume and test power simultaneously. The pre-generated test sets are divided into two groups based on the number of unspecified bits in each test set. Test compression procedure is applied only to the group of test sets which contain more unspecified bits and the power reduction technique is applied to the remaining test sets. In the proposed approach, the unspecified bits in the pre-generated test sets are selectively mapped with 0s or 1s based on their effectiveness in reducing the test data volume and power consumptions. We also present a simple decoder architecture for on-chip decompression. Experimental results on ISCAS’89 benchmark circuits demonstrate the effectiveness of the proposed technique compared with other test-independent compression techniques.

Transition Analysis for Power Reduction in SoC

Size and complexity have been major issues for System-on-a-Chip (SoC) testing. Transition analysis plays a significant role in power consideration of SoC testing. Transition is directly propositional to the power. This paper is based on finding transition calculation to achieve minimum power consideration. Transition study is applied for both specified and unspecified bits. The unspecified bits are specified by using X filling techniques like Zero filling and One filling algorithm. Transition analysis is considered for different partition length. The proposed method is successfully tested on ISCAS89 benchmark circuits which achieve minimum power consideration

Efficient don't care filling and scan chain masking for low-power testing

This paper addresses two methods for reducing power consumption during testing. The first one is to assign suitable values to the unspecified bits (don’t cares) in the test patterns so that both static and dynamic power are reduced. The second technique discusses the issue of blocking pattern selection for reducing power consumption during circuit testing in a scan-based approach. The blocking pattern is used to prevent the scan chain transitions from reaching circuit inputs. This, though reduces dynamic power significantly, can result in quite an increase in the leakage power. We have presented a novel approach to select a blocking pattern using genetic algorithm and use it properly so that both dynamic and leakage power are reduced.

Efficient Test Data Compression Achieved by Reduced Control Code

Test data compression is a major scenario in all system-on-a-chip (SOC) designs for reducing the volume of the test data. The volume of the test data directly affects the cost of SOC design. Many compression techniques have been proposed to achieve better compression. Although all the techniques proposed are applied only for those test data having larger number of unspecified bits (X's), it is not able to achieve better compression for those test data having larger number of specified values (0's and 1's). In this paper a new compression technique is proposed to achieve higher compression for test data having larger number of specified values by reducing the size of the control code. In this method the length of the control code is significantly reduced. The proposed technique is applied on ISCAS’89 benchmark circuits and its results are compared with existing method

An Efficient Compatibility-Based Test Data Compression and Its Decoder Architecture

Test data compression is an effective methodology for reducing test data volume and testing time. A novel compatibility-based test data compression method is presented in this paper. With the high compression efficiency of extended frequency-directed run length coding algorithm, the proposed method groups the test vectors that have least incompatible bits and amalgamates them into a single vector by assigning 1 or 0 to unspecified bits and c to incompatible bits. Three runs of 1, 0 and c can be encoded simultaneously. In addition, the corresponding decoder architecture with low hardware overhead has been developed. To evaluate the effectiveness of the proposed approach, in experiments, it is applied to the International Symposium on Circuits and Systems’ benchmark circuits. The experiments results show that the proposed algorithm gets a higher compression ratio than the conventional algorithms.

Squashing code size in microcoded IPs while delivering high decompression speed

Microcoded customized IPs offer superior performance and direct programmability of micro-architectural structures compared to instruction-based processors, yet at the cost of drastically enlarged code sizes. Code compression can deliver size reductions but necessitates attention to performance issues, so that the performance benefits of microcoded IPs are not squandered in the process. To attain this goal, we propose in this paper a fast code compression technique through exploiting the fact that the microcodes contain a sizable amount of unspecified bits. Although the values and the positions of the specified bits are highly irregular, the proposed technique can still flexibly and precisely fill in these fully specified bits through utilizing a linear network. The linear property inherent in the compression strategy in turn enables the development of an extremely low-overhead decompression engine. At runtime, the decompressed code can be generated in such a way that all the specified bits can be filled as required by a fixed-bandwidth XOR network. The combination of the proposed flexible XOR-based network with a minimum two-level storage for highly specified fields, such as immediate values, offers utmost code compression, attained within a negligible amount of performance and hardware overhead.

On Test Generation With Test Vector Improvement

We investigate the introduction of a new step, referred to as test vector improvement, into test generation processes. After a fully specified test vector or a partially specified test cube t is generated at an arbitrary iteration of the test generation process, the test vector improvement step modifies t so as to increase the number of yet-undetected target faults that t detects. This is done in this paper using a simulation-based process. We show that even if t was generated using dynamic test compaction heuristics, it is possible to improve t further. When t is partially specified to accommodate test data compression, the test vector improvement step does not change the number of unspecified bits of t. The final result is a smaller test set and/or a higher fault coverage (if the test generation process does not detect all the detectable faults).

Test Set Generation with a Large Number of Unspecified Bits Using Static and Dynamic Techniques

This work presents two new methods for the generation of test sets with a small number of specified bits. Such type of test sets have been proven beneficial to a large number of test-related applications such as deterministic BIST, low power testing and test set enrichment. The first technique is static, since it considers an initial test set which attempts to relax via test replacement with tests of similar coverage but with fewer specified bits. The second technique is dynamic; it generates a test set from a zero base using a hierarchical fault-compatibility algorithm. Both methods are applicable to any enumerative fault method (linear to the circuit size). The experiments performed using the stuck-at fault model demonstrate the superiority of the proposed methods over comparable existing techniques, in reducing the total number of specified bits per generated test set. The applicability of the generated relaxed test sets is demonstrated for one, out of the many, possible applications, that of deterministic test set embedding. A general framework that integrates the proposed relaxation methods in two popular LFSR-based test set embedding schemes (full and partial reseeding), along with a systematic exploration of related parameters, is proposed. The obtained results show significant reductions in seed storage requirements.

Test data compression using extended frequency-directed run length code based on compatibility

A new test data compression method is presented. Based on the fact that adjacent test vectors in a test set have least incompatible bits, test vectors are grouped and amalgamated into a vector by assigning 1 or 0 to unspecified bits and c to incompatible bits. Extended frequency-directed run length based on compatibility (EFDR-BC) is used to encode the merged test vector. EFDR-BC can encode strings of 1s, 0s, and cs. The numbers of test vectors, incompatible bits and values of incompatible bits in a group make up the group head code. Experiments with the test sets of the ISCAS 89 benchmark circuit show that the method can achieve higher compression ratio.

A test set embedding approach based on twisted-ring counter with few seeds

Test data storage, test application time and test power dissipation increase dramatically for single stuck-at faults while tens of million gates are integrated in a System-on-a-Chip (SoC), which makes implementing fault testing for embedded cores based SoC become a challenging task. To further reduce test data storage, test application time and test power dissipation, this paper presents a new test set embedding approach based on twisted-ring counter (TRC) with few seeds. This approach includes two improvements. The first is that an efficient seed-selection algorithm is employed to exploit the high-density unspecified bits in the deterministic test set and so the test data storage for complete coverage of single stuck-at faults is minimized. The second is that a novel test-sequence-reduction scheme based on shifting seeds is proposed to reduce test application time that in turn reduces test power dissipation. Compared with the conventional approach, experiments on ISCAS’89 benchmark circuits show that the proposed approach requires 65% less test data storage, 68% shorter test application time and 67% less test power dissipation. Moreover, its hardware overhead is very small.

A New Scan Partition Scheme for Low-Power Embedded Systems

A new scan partition architecture to reduce both the average and peak power dissipation during scan testing is proposed for low-power embedded systems. In scan-based testing, due to the extremely high switching activity during the scan shift operation, the power consumption increases considerably. In addition, the reduced correlation between consecutive test patterns may increase the power consumed during the capture cycle. In the proposed architecture, only a subset of scan cells is loaded with test stimulus and captured with test responses by freezing the remaining scan cells according to the spectrum of unspecified bits in the test cubes. To optimize the proposed process, a novel graph-based heuristic to partition the scan chain into several segments and a technique to increase the number of don't cares in the given test set have been developed. Experimental results on large ISCAS89 benchmark circuits show that the proposed technique, compared to the traditional full scan scheme, can reduce both the average switching activities and the average peak switching activities by 92.37% and 41.21%, respectively.

A New Scan Architecture for Both Low Power Testing and Test Volume Compression Under SOC Test Environment

A new scan architecture for both low power testing and test volume compression is proposed. For low power test requirements, only a subset of scan cells is loaded with test stimulus and captured with test responses by freezing the remaining scan cells according to the distribution of unspecified bits in the test cubes. In order to optimize the proposed process, a novel graph-based heuristic is proposed to partition the scan chains into several segments. For test volume reduction, a new LFSR reseeding based test compression scheme is proposed by reducing the maximum number of specified bits in the test cube set, s max, virtually. The performance of a conventional LFSR reseeding scheme highly depends on s max. In this paper, by using different clock phases between an LFSR and scan chains, and grouping the scan cells by a graph-based grouping heuristic, s max could be virtually reduced. In addition, the reduced scan rippling in the proposed test compression scheme can contribute to reduce the test power consumption, while the reuse of some test results as the subsequent test stimulus in the low power testing scheme can reduce the test volume size. Experimental results on the largest ISCAS89 benchmark circuits show that the proposed technique can significantly reduce both the average switching activity and the peak switching activity, and can aggressively reduce the volume of the test data, with little area overhead, compared to the previous methods.

Low Cost Scan Test by Test Correlation Utilization

Scan-based testing methodologies remedy the testability problem of sequential circuits; yet they suffer from prolonged test time and excessive test power due to numerous shift operations. The correlation among test data along with the high density of the unspecified bits in test data enables the utilization of the existing test data in the scan chain for the generation of the subsequent test stimulus, thus reducing both test time and test data volume. We propose a pair of scan approaches in this paper; in the first approach, a test stimulus partially consists of the preceding stimulus, while in the second approach, a test stimulus partially consists of the preceding test response bits. Both proposed scan-based test schemes access only a subset of scan cells for loading the subsequent test stimulus while freezing the remaining scan cells with the preceding test data, thus decreasing scan chain transitions during shift operations. The proposed scan architecture is coupled with test data manipulation techniques which include test stimuli ordering and partitioning algorithms, boosting test time reductions. The experimental results confirm that test time reductions exceeding 97%, and test power reductions exceeding 99% can be achieved by the proposed scan-based testing methodologies on larger ISCAS89 benchmark circuits.

A Novel ATPG Method for Capture Power Reduction during Scan Testing

High power dissipation can occur when the response to a test vector is captured by flip-flops in scan testing, resulting in excessive IR drop, which may cause significant capture-induced yield loss in the DSM era. This paper addresses this serious problem with a novel test generation method, featuring a unique algorithm that deterministically generates test cubes not only for fault detection but also for capture power reduction. Compared with previous methods that passively conduct X-filling for unspecified bits in test cubes generated only for fault detection, the new method achieves more capture power reduction with less test set inflation. Experimental results show its effectiveness.

Maxx: Test Pattern Optimisation with Local Search Over an Extended Logic

In the electronic computer-aided design area, the test generation problem consists in finding an input vector test for some possible diagnosis (a set of faults) of a digital circuit. Such tests may have some unspecified Primary Inputs (i.e. bits are assigned neither 0 nor 1). In fact, for many purposes, minimally specified tests (or patterns) are preferred. Hence, we have the test pattern optimisation (TPO) problem where the goal is to obtain a test with the maximum number of unspecified bits. In this paper we discuss different modelling approaches and present a TPO tool (Maxx) that substantially outperforms others by combining Branch-and-Bound and local search over distinct models. We apply the usual branch-and-bound search on CLP(FD) over a simple, yet incomplete, logic. A complementary Local Search is performed over an extended model, trying to improve an already computed solution by exploring an extended solution space thanks to the use of an extended logic (too complex for constraint solving). Such extended logic considers sets of dependencies on specified input values, keeping track of sources of unspecified values and their inversion parities. This allows modelling a number of alternative test vectors by unspecification of each possible input bit, thus being able to obtain an improved test vector in linear time. This paper shows, for TPO, that adapting constraint propagation with results obtained from local search outperforms the use of each of these techniques alone, obtaining significantly better results than those obtained with a highly efficient tool based on an integer linear programming formulation on a propositional satisfiability model.