An Efficient Compatibility-Based Test Data Compression and Its Decoder Architecture

Abstract

Test data compression is an effective methodology for reducing test data volume and testing time. A novel compatibility-based test data compression method is presented in this paper. With the high compression efficiency of extended frequency-directed run length coding algorithm, the proposed method groups the test vectors that have least incompatible bits and amalgamates them into a single vector by assigning 1 or 0 to unspecified bits and c to incompatible bits. Three runs of 1, 0 and c can be encoded simultaneously. In addition, the corresponding decoder architecture with low hardware overhead has been developed. To evaluate the effectiveness of the proposed approach, in experiments, it is applied to the International Symposium on Circuits and Systems’ benchmark circuits. The experiments results show that the proposed algorithm gets a higher compression ratio than the conventional algorithms.