Unsigned Numbers Research Articles

Energy-Efficient Low-Latency Signed Multiplier for FPGA-Based Hardware Accelerators

Multiplication is one of the most extensively used arithmetic operations in a wide range of applications, such as multimedia processing and artificial neural networks. For such applications, multiplier is one of the major contributors to energy consumption, critical path delay, and resource utilization. These effects get more pronounced in field-programmable gate array (FPGA)-based designs. However, most of the state-of-the-art designs are done for ASIC-based systems. Furthermore, a few field-programmable gate array (FPGA)-based designs that exist are largely limited to unsigned numbers, which require extra circuits to support signed operations. To overcome these limitations for the FPGA-based implementations of applications utilizing signed numbers, this letter presents an area-optimized, low-latency, and energy-efficient architecture for an accurate signed multiplier. Compared to the Vivado area-optimized multiplier IP, our implementations offer up to 40.0%, 43.0%, and 70.0% reduction in terms of area, latency, and energy, respectively. The RTL implementations of our designs will be released as an open-source library at https://cfaed.tu-dresden.de/pd-downloads.

Area-Optimized Accurate and Approximate Softcore Signed Multiplier Architectures

Multiplication is one of the most extensively used arithmetic operations in a wide range of applications. In order to provide resource-efficient and high-performance multipliers, previous works have proposed different designs of accurate and approximate multipliers-mainly for ASIC-based systems. However, the architectural differences between ASICs- and FPGA-based systems limit the effectiveness of these multipliers for FPGA-based systems. Moreover, most of these multiplier designs are valid only for unsigned numbers. To bridge this gap, we propose a novel implementation technique for designing resource-efficient and low-power accurate and approximate signed multipliers which are optimized for FPGA-based systems. Compared to Vivado's area-optimized multiplier IPs, the designs obtained using our proposed technique occupy 47 to 63 percent less area (Lookup Tables). To accelerate further research in this direction and reproduce the presented results, the RTL and behavioral models of our proposed methodology are available as an open-source library. <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sup> 1.Online. [Available]: https://cfaed.tu-dresden.de/pd-downloads.

Analysis of 32 × 32-Bit Parallel Pipeline Multiplier Using In-Built Register Transfer Level Testing Approach

This paper presents a design and implementation of Fixed Point Ultra High Throughput Multiplier (UHTM) using parallel pipeline architecture for both signed and unsigned numbers to improve the throughput of the VLSI SoC design. Here backend issues are addressed in the front end RTL design itself hence this reduces the testing time by detecting all possible defects. In this paper RTL coding style is realized with respect to FPGA design. In an FPGA design inbuilt DSP blocks is used for arithmetic (multiplication) operations which will achieve the higher frequency of operation. In addition power and timing optimization techniques are also addressed to reduce dynamic power. The multiplier hardware design of 32×32 bit UHTM is synthesized in FPGA and compared with the previous works. As a result of this, 32×32 multiplier achieves the throughput of 15552 Mbps at 243 MHz, 64 bits per clock cycle output in FPGA and 32 Gbps at 1.2 GHz, 64 bits per clock cycle in ASIC, obtains the best hardware efficiency in terms of area in the FPGA area utilization of 1264 ALUTs, 2811 FFs in the Cyclone V5CSXFC6D6F3117 device with First in First out latency of ten clock cycles at the rate of 243 MHz clock frequency. The Structural realization and analysis pertaining to timing, area and power are implemented in Cyclone V 5CSXFC6D6F3117 FPGA and ASIC 28 nm technology.

Booth Algorithm with Implementation of UART Module using FPGA

FPGA gives high level of flexibility to the user to rapidly construct and test any hardware. It has a lot of gates which are used depending upon the hardware to be implemented. These project aims at designing Booth multiplier using VHDL for signed bit multiplication in FPGA for high speed operations, developed and implemented of UART module required to enable two-way communication between the DE-2 board and computer. It is also designed GUI interface using MATLAB for sending data and enable the output of the process result to be displayed. The Booth multiplier was implemented using the algorithm in both signed and unsigned number and the input and output of the multiplication was successfully achieved and confirmed through simulation. The GUI was implemented and tested, which UART module also performed well for transmitting and receiving of 8-bit width data. In general, the objective of this project was successfully achieved, which, the result of the component part were able to be tested.

A Multiplication Algorithm

Paper Setup must be in A4 size with Margin: Top 0.7”, Bottom 0.7”, Left 0.65”, 0.65”, Gutter 0”, and Gutter Position Top. Pap Abstract: Multiplication is common arithmetic operation in ALU. Many algorithm are proposed for multiplying two unsigned numbers in literature. This paper proposes algorithm to multiply two unsigned binary numbers of any size. The most significant two bits are used to determine the partial product by bit inspection. The rest of partial products are obtained by suitably shifting the previous partial products and adding the terms involving remainders. The remainder is obtained by taking one bit at a time from the MSB-2 position assuming numbers are indexed from zero in LSB to maximum-1 in MSB. The multiplication process is performed as series of additions, shifts in this method. The proposed method is simulated in Quartus2 Toolkit. It is compared to the in-built multiplication process of the tool. A timing improvement of 9.5% with comparable power consumption is obtained with same pin count.

Design and implementation of low power and high speed multiplier using quaternary carry look-ahead adder

Need of Digital Signal Processing (DSP) systems which is embedded and portable has been increasing as a result of the speed growth of semiconductor technology. Multiplier is a most crucial part in almost every DSP application. So, the low power, high speed multipliers is needed for high speed DSP. Array multiplier is one of the fast multiplier because it has regular structure and it can be designed very easily. Array multiplier is used for multiplication of unsigned numbers by using full adders and half adders. It depends on the previous computations of partial sum to produce the final output. Hence, delay is more to produce the output. In the previous work, Complementary Metal Oxide Semiconductor (CMOS) Carry Look-ahead Adders (CLA) and CMOS power gating based CLA are used for maximizing the speed of the multiplier and to improve the power dissipation with minimum delay. CMOS logic is based on radix 2(binary) number system. In arithmetic operation, major issue corresponds to carry in binary number system. Higher radix number system like Quaternary Signed Digit (QSD) can be used for performing arithmetic operations without carry. The proposed system designed an array multiplier with Quaternary Signed Digit number system (QSD) based Carry Look-Ahead Adder (CLA) to improve the performance. Generally, the quaternary devices require simpler circuit to process same amount of data than that needed in binary logic devices. Hence the Quaternary logic is applied in the CLA to improve the speed of adder and high throughput. In array multiplier architecture, instead of full adders, carry look-ahead adder based on QSD are used. This facilitates low consumption of power and quick multiplication. Tanner EDA tool is used for simulating the proposed multiplier circuit in 180 nm technology. With respect to area, Power Delay Product (PDP), Average power proposed QSD CLA multiplier is compared with Power gating CLA and CLA multiplier.

Программное обеспечение для системы архивирования данных ЛИУ-20

The control system of the X-ray complex LIA-20 is based on the Tango Controls framework. Data archiving subsystem HDB++ was improved during the work for efficient storage of waveforms. PostgreSQL DBMS support as a storage was added. PostgreSQL extension “pguint” for unsigned numbers support was modified to support the binary transfer mode during this work. Performance testing of the modified “pguint” extension and the new DBMS interface was performed. This solution allowed to significantly increase the performance of HDB++, reduce the amount of data stored in the database, as well as remove restrictions on the size of the stored data.

Review of Rounding Based Approximate Multiplier (ROBA) For Digital Signal Processing

The fundamental idea of adjusting put together estimated multiplier depends with respect to adjusting of numbers. This multiplier can be connected for both marked and unsigned numbers. In this paper contemplated an Rounding Based Approximate Multiplier that is fast yet vitality effective. The methodology is to round the operands to the closest example of two. Along these lines the computational concentrated piece of the augmentation is excluded improving rate and vitality utilization at the cost of a little mistake. This methodology is appropriate to both marked and unsigned augmentations. The productivity of the ROBA multiplier is assessed by contrasting its execution and those of some rough and precise multipliers utilizing distinctive plan parameters.

Reversible Logic Multipliers: Novel Low-cost Parity-Preserving Designs

Reversible logic is one of the new paradigms for power optimization that can be used instead of the current circuits. Moreover, the fault-tolerance capability in the form of error detection or error correction is a vital aspect for current processing systems. In this paper, as the multiplication is an important operation in computing systems, some novel reversible multiplier designs are proposed with the parity-preserving property which will be useful for error detection. At first, two optimal signed serial multipliers are presented based on the Booth’s algorithm and its enhanced version called the K-algorithm, utilizing the new arrangements of reversible gates. Then, another low-cost serial multiplier is proposed based on the conventional Add & Shift method to be utilized in the applications in which unsigned numbers are used. Finally, a new signed parallel multiplier is proposed based on the Baugh-Wooley method that is useful for speed-critical applications. The comparative results showed that the proposed multipliers are much better than the existing designs regarding the main criterions used in reversible logic circuits including quantum cost, gate count, constant inputs, and garbage outputs.

A Novel Design of a Multiplier Using Reversible Ternary Gates

ABSTRACT Reversible ternary circuit design is now being taken into consideration for its application within the quantum computer and other technologies associated with the nanotechnology domain, in addition to the advantages of the ternary logic application as opposed to binary logic. Multiplier circuit is one of the most important computing circuit in the ALU. Therefore, the circuit optimization for the multiplication will lead to efficient processor. In this paper, the reversible circuit for multiplication of two unsigned two-digit ternary numbers has been proposed. To construct reversible ternary multiplier, a new component termed TPPG with the quantum cost of 13 for partial product generation was proposed. In addition, we have introduced four new blocks of reversible ternary adder with the quantum cost of 11, 10, 7, 5 and one constant input, which can be used in the proposed multiplier circuit. We attempted to optimize the design of the circuits in terms of quantum cost, a number of primitive gates, constant inputs, and garbage outputs as far as possible. To realize all proposed circuits, one-qutrit shift gates and two-qutrit Muthukrishnan-Stroud gates were used.

Refinements of the Bell and Stirling numbers

‎‎We introduce new refinements of the Bell‎, ‎factorial‎, ‎and unsigned Stirling numbers of the first and second kind that unite the derangement‎, ‎involution‎, ‎associated factorial‎, ‎associated Bell‎, ‎incomplete Stirling‎, ‎restricted factorial‎, ‎restricted Bell‎, ‎and $r$-derangement numbers (and probably more!)‎. ‎By combining methods from analytic combinatorics‎, ‎umbral calculus‎, ‎and probability theory‎, ‎we derive several recurrence relations and closed form expressions for these numbers‎. ‎By specializing our results to the classical case‎, ‎we recover explicit formulae for the Bell and Stirling numbers as sums over compositions‎.

Designing of a reversible fault tolerant booth multiplier

Conventional logic dissipates more power by losing bits of information whereas reversibility recovers bit loss from the unique input-output mapping. This paper presents the design of a reversible fault tolerant booth multiplier which can multiply both signed and unsigned numbers. The proposed circuit tolerant designed using only fault tolerant reversible gates. Thus the entire scheme inherently becomes fault tolerant. Several theorems on the numbers of gates, garbage outputs, quantum cost of the proposed design have been presented to show the efficiency of the design. The result analysis shows that the proposed design is optimized in terms of all cost parameters. The simulation of the proposed circuit verifies the correctness of the circuit.Bangladesh J. Sci. Ind. Res.53(3), 199-204, 2018

Statistical Analysis of Torus and Kink Instabilities in Solar Eruptions

Abstract A recent laboratory experiment of ideal magnetohydrodynamic instabilities revealed four distinct eruption regimes readily distinguished by the torus instability (TI) and helical kink instability (KI) parameters. To establish its observational counterpart, we collected 38 solar flares (stronger than GOES-class M5 in general) that took place within 45° of disk center during 2011–2017, 26 of which are associated with a halo or partial halo coronal mass ejection (CME; i.e., ejective events), while the others are CME-less (i.e., confined events). This is a complete sample of solar events satisfying our selection criteria detailed in the paper. For each event, we calculate a decay index n of the potential strapping field above the magnetic flux rope (MFR) in and around the flaring magnetic polarity inversion line (a TI parameter) and the unsigned twist number T w of the nonlinear force-free field lines forming the same MFR (a KI parameter). We then construct an n–T w diagram to investigate how the eruptiveness depends on these parameters. We find that (1) T w appears to play little role in discriminating between confined and ejective events; (2) the events with n ≳ 0.8 are all ejective, and all confined events have n ≲ 0.8. However, n ≳ 0.8 is not a necessary condition for eruption because some events with n ≲ 0.8 also erupted. In addition, we investigate the MFR’s geometrical parameters, apex height, and distance between footpoints, as a possible factors for the eruptiveness. We briefly discuss the difference of the present result for solar eruptions with that of the laboratory result in terms of the role played by magnetic reconnection.

Restricted Stirling and Lah number matrices and their inverses

Given R⊆N let {nk}R, [nk]R, and L(n,k)R count the number of ways of partitioning the set [n]:={1,2,…,n} into k non-empty subsets, cycles and lists, respectively, with each block having cardinality in R. We refer to these as the R-restricted Stirling numbers of the second kind, R-restricted unsigned Stirling numbers of the first kind and the R-restricted Lah numbers, respectively. Note that the classical Stirling numbers of the second kind, unsigned Stirling numbers of the first kind, and Lah numbers are {nk}={nk}N, [nk]=[nk]N and L(n,k)=L(n,k)N, respectively.It is well-known that the infinite matrices [{nk}]n,k≥1, [[nk]]n,k≥1 and [L(n,k)]n,k≥1 have inverses [(−1)n−k[nk]]n,k≥1, [(−1)n−k{nk}]n,k≥1 and [(−1)n−kL(n,k)]n,k≥1 respectively. The inverse matrices [{nk}R]n,k≥1−1, [[nk]R]n,k≥1−1 and [L(n,k)R]−1n,k≥1 exist and have integer entries if and only if 1∈R. We express each entry of each of these matrices as the difference between the cardinalities of two explicitly defined families of labeled forests. In particular the entries of [{nk}[r]]−1n,k≥1 have combinatorial interpretations, affirmatively answering a question of Choi, Long, Ng and Smith from 2006.If we have 1,2∈R and if for all n∈R with n odd and n≥3, we have n±1∈R, we additionally show that each entry of [{nk}R]n,k≥1−1, [[nk]R]−1n,k≥1 and [L(n,k)R]n,k≥1−1 is up to an explicit sign the cardinality of a single explicitly defined family of labeled forests. With R as before we also do the same for restriction sets of the form R(d)={d(r−1)+1:r∈R} for all d≥1. Our results also provide combinatorial interpretations of the kth Whitney numbers of the first and second kinds of Πn1,d, the poset of partitions of [n] that have each part size congruent to 1 mod d.

Analysis and comparison of fast multiplier circuits based on different parameters

Digital multiplier circuits are used in computers. A multiplier is an electronic circuit used in digital electronics to multiply two binary numbers. Multiplier circuits are used in ALU for binary multiplication of signed and unsigned numbers. The delay, area and power consumption are the 3 most important design specifications a chip designer has to consider. Delay of the circuit is directly proportional to the delay of a multiplier. Increased delay in the multiplier leads to higher delay in the circuit. Therefore research is carried out as to how to reduce the delay of the multiplier block so as to reduce the delay of whole circuit. The main purpose is to deal with high speed and lower power consumption even after decreasing the silicon area. This makes them well-suited for numerous complex and convenient VLSI circuit implementations. The fact however, remains that area and speed are two contradictory performance restrictions. Hence, increase in speed always results in the use of more and complex hardware. Different arithmetic techniques can be used to implement different multiplier circuits. The focus of this paper is to implement various multiplier circuit and compare them. The timing signals can be observed using software such as Modelsim and Xilinx.

Modified stochastic fragmentation of an interval as an ageing process

We study a stochastic model based on modified fragmentation of a finite interval. The mechanism consists of cutting the interval at a random location and substituting a unique fragment on the right of the cut to regenerate and preserve the interval length. This leads to a set of segments of random sizes, with the accumulation of small fragments near the origin. This model is an example of record dynamics, with the presence of ‘quakes’ and slow dynamics. The fragment size distribution is a universal inverse power law with logarithmic corrections. The exact distribution for the fragment number as function of time is simply related to the unsigned Stirling numbers of the first kind. Two-time correlation functions are defined, and computed exactly. They satisfy scaling relations, and exhibit aging phenomena. In particular, the probability that the same number of fragments is found at two different times is asymptotically equal to when and the ratio is fixed, in agreement with the numerical simulations. The same process with a reset impedes the aging phenomenon-beyond a typical time scale defined by the reset parameter.

HARDWARE IMPLEMENTATION OF METHODOLOGIES OF FIXED POINT DIVISION ALGORITHMS

Abstract This paper describes the hardware implementation methodologies of fixed point binary division algorithms. The implementations have been extended for the execution of the reciprocal of the binary numbers. Radix-2 (binary) implementations of digit recurrence and multiplicative based methods have been considered for comparison. Functionality of the algorithms have been verified in Verilog hardware description language (HDL) and synthesized in Xilinx ISE 8.2i targeting the device xc4vlx15-12sf363 of Virtex4 family. Implementation was done for both signed and unsigned number systems, having bit width of operands vary as an exponential function of 2n, where n=2 to 5. Performance parameters have been calculated in terms of clock frequency, FPGA slice utilization, latency and power consumption. Implementation results indicate that multiplicative based algorithm is superior in terms of latency, while digit recurrence algorithms are consuming low power along-with less area overhead.

An Efficient Component for Designing Signed Reverse Converters for a Class of RNS Moduli Sets of Composite Form $\{2^{k}, 2^{P}-1\}$

The application of residue number system (RNS) to digital signal processing lies in the ability to operate on signed numbers. However, the available RNS-to-binary (reverse) converters have been designed for unsigned numbers, which means that they do not produce signed outputs. Usually, some additional circuits are introduced at the output of the reverse converter to map the unsigned generated output into a signed number representation. This paper proposes a novel method to design reverse converters with signed output for a class of RNS moduli sets of composite form $\{2^{k}, 2^{P}-1\}$ . The structure of the modulo adder used in the last stage of the proposed converters is modified in order to reuse the internal circuits to produce the signed output. This adder component is especially designed for achieving reverse converters with signed output, imposing very low area and delay overheads compared with unsigned converters. The proposed approach is applied to design reverse converters for different moduli sets and to implement application specific integrated circuits. Experimental results show that for a 4-moduli converter, the proposed design can outperform the traditional method to obtain signed outputs by improving the delay, chip-area, and energy consumption by up to 9%, 21%, and 35%, respectively.

Superscalar pipelined inner product computation unit for signed unsigned number

Summary In this paper, we proposed superscalar pipelined inner product computation unit for signed-unsigned number operating at 16 GHz. This is designed using five stage pipelined operation with four 8 × 8 multipliers operating in parallel. Superscalar pipelined is designed to compute four 8 × 8 products in parallel in three clock cycles. In the fourth clock cycle of the pipeline operation, two inner products are computed using two adders in parallel. Fifth stage of the pipeline is designed to compute the final product by adding two inner partial products. Upon the pipeline is filled up, every clock cycle the new product of 16 × 16-bit signed unsigned number is obtained. The worst delay measured among the pipeline stage is 0.062 ns, and this delay is considered as the clock cycle period. With the delay of 0.062 ns clock cycle period, the pipeline stage can be operated with 16 GHz synchronous clock signal. Each superscalar pipeline stage is implemented using 45 nm CMOS process technology, and the comparison of results shows that the delay is decreased by 38%, area is reduced by 45% and power dissipation is saved by 32%.

Realization of Efficient Multiplier for Low Power Biomedical Signal Processing System-on-Chip Design for Portable ECG Monitoring Systems

This paper introduces a framework for the implementation of high throughput Multiplier for low Power Biomedical Signal Processing System-on-Chip (SoC) design for Portable ECG Monitoring Systems. In this paper the realization of Efficient Multiplier for the proposed architecture in the implementation of the Biomedical Signal SoC monitoring system is presented. Since the multiplier is the part of the processor core which needs more attention and a modified approach of generating partial product for successful multiplication of the bit streams has been presented. The proposed SoC incorporates a new architecture using the booth multiplier and sign extension multiplier for 4 bit, 8 bit and 16 bit performing multiplication on both signed and unsigned number. The implementation is further extended on the radix application of booth multiplier and sign extension method. Different parameters have been compared for both signed and unsigned multiplier. The implementation is done through VHDL on Quartus II synthesizer for Cyclone II family.