Analysis of 32 × 32-Bit Parallel Pipeline Multiplier Using In-Built Register Transfer Level Testing Approach

Abstract

This paper presents a design and implementation of Fixed Point Ultra High Throughput Multiplier (UHTM) using parallel pipeline architecture for both signed and unsigned numbers to improve the throughput of the VLSI SoC design. Here backend issues are addressed in the front end RTL design itself hence this reduces the testing time by detecting all possible defects. In this paper RTL coding style is realized with respect to FPGA design. In an FPGA design inbuilt DSP blocks is used for arithmetic (multiplication) operations which will achieve the higher frequency of operation. In addition power and timing optimization techniques are also addressed to reduce dynamic power. The multiplier hardware design of 32×32 bit UHTM is synthesized in FPGA and compared with the previous works. As a result of this, 32×32 multiplier achieves the throughput of 15552 Mbps at 243 MHz, 64 bits per clock cycle output in FPGA and 32 Gbps at 1.2 GHz, 64 bits per clock cycle in ASIC, obtains the best hardware efficiency in terms of area in the FPGA area utilization of 1264 ALUTs, 2811 FFs in the Cyclone V5CSXFC6D6F3117 device with First in First out latency of ten clock cycles at the rate of 243 MHz clock frequency. The Structural realization and analysis pertaining to timing, area and power are implemented in Cyclone V 5CSXFC6D6F3117 FPGA and ASIC 28 nm technology.