Universal Mobility Research Articles

SOCIAL NETWORKS AS A LANGUAGE TEACHING TOOL

Social networks constitute an intrinsic part of our lives, not only in private aspects, but also professional and academic ones. Digitalisation in various professional and scientific fields, web 2.0, universal mobility and the growing use of multimedia tools in the classroom have led to the use of social networks as teaching material and tools.
 In this work, the main social networks suitable for language teaching will be illustrated and various possibilities for their use will be indicated to derive maximum benefit from them in the classroom or during the student's independent study. Activities that may include the use of digital applications and the ways in which these platforms can be inserted into the different phases of the lesson will be indicated.
 Finally, various practical examples of the inclusion of social networks in the classroom will be given, accompanied by intentional reflections to encourage language teachers to include web 2.0 tools among their working methods.

Dominant scattering mechanism in SiC MOSFET: comparative study of the universal mobility and the theoretically calculated channel mobility

The universal mobility in SiC MOSFETs is investigated and compared with the theoretically calculated channel mobility. From an analysis of channel mobility of SiC MOSFETs with sufficiently reduced Coulomb scattering centers, it is quantitatively shown that η, which determines effective electric fields Eeff (=q(Ndpl + η Ns)/εs), should be set to 0.26 to express the mobility universally. Acoustic-phonon scattering-limited mobility, intervalley-scattering-limited mobility, and roughness-scattering-limited mobility are calculated and compared with the universal mobility. Consequently, it is shown that acoustic phonon scattering is dominant in a wide Eeff range, whereas roughness scattering has a slight effect in a high Eeff range, and the influence of intervalley-scattering is limited throughout the Eeff range. In particular, it is shown that acoustic phonon scattering between the 1st conduction band minima (CBM) and 2nd CBM, which exists 120 meV above the 1st CBM, greatly limits mobility of SiC MOSFETs.

A formação e o ensino do turismo acessível: O caso das escolas profissionais do Faial, Pico e de São Jorge

A temática da acessibilidade universal no turismo, também conhecido como turismo acessível, inclusivo entre outras designações, está presente nos planos, discursos e apresentações das mais diversas entidades, organizações e instituições. A educação e formação no turismo em geral, e nas temáticas da acessibilidade e mobilidade universal no turismo em particular, assumem uma grande importância para o desenvolvimento do setor como em recursos humanos qualificados. O presente artigo investiga se as temáticas acima mencionadas estão presentes no Catálogo Nacional de Qualificações, em particular nas áreas de formação ligadas ao setor do turismo. Para este efeito, são apresentados os principais resultados de um inquérito aplicado aos formandos dos cursos de turismo das escolas profissionais do Faial, Pico e de São Jorge nos Açores. Constata-se que num total de 524 Unidades de Formação de Curta Duração existentes no Catálogo Nacional das Qualificações relativo ao setor do turismo, 5 abordam as temáticas do turismo acessível e inclusivo. 66 dos 107 inquiridos referem não ter tido qualquer módulo ou formação na área, o que corresponde a mais de 60%.

Design and Analysis of High Mobility Enhancement-Mode 4H-SiC MOSFETs Using a Thin-SiO2/Al2O3Gate-Stack

High-performance 4H-SiC MOSFETs have been fabricated, having a peak effective mobility of 265 cm2/ $\text{V}\,\cdot $ s, and a peak field effect mobility of 154 cm2/V s, in 2- $\mu $ m gate length MOSFETs. The gate-stack was designed to minimize interface states and comprised a 0.7-nm thermally grown SiO2 on 4H-SiC, followed by Al2O3 and a metal gate contact. In this way, carbon remaining following SiC oxidation is significantly reduced. A density of interface traps in the range of $6 \times 10^{11} - 5 \times 10^{10}$ cm−2eV−1 is also obtained. Temperature-dependent electrical data reveal that the high mobility results from conduction being phonon-limited, rather than Coulomb-limited. Furthermore, universal mobility in these 4H-SiC MOSFETs is shown to be up to 50% of that observed in the Si devices. Expressions for electric field-dependent contributions to mobility are presented. A steep subthreshold slope of 127 mV/decade indicates low electrical defect density. A temperature coefficient of −4.6 mV/K in threshold voltage is similar to that in the Si MOSFETs.

From universalism to selectivity? The background, discourses and ideas of recent early childhood education and care reforms in Finland

ABSTRACTUniversal public childcare for children under seven has been central in Finland since the mid-1990s, capacitating both gender equality and children’s human capital and wellbeing. In 2015, as a further step in the development of this system, early learning and childhood pedagogy was strengthened through the early childhood education and care (ECEC) reform (statute 580/2015). Some months later, however, the right to full-day ECEC was restricted to children with employed parents (statute 108/2016). This paper discusses the objectives, framing and ideational drivers of these reforms on the basis of government bills and parliamentary debates. We argue that the development reflects a shift in emphasis from a universal and child-oriented social mobility ECEC rationale to a more austere rationale focussing on parents’ and notably mothers’ employment. We believe that the reforms will have negative effects on the quality of ECEC and increase inequalities in children’s human capital and learning.

A Universal IP Mobility Framework with Compulsory Route Optimization for MIPv6 and PMIPv6 Coexistence

With the almost ubiquitous availability of wireless networks and the increasing communication capabilities of portable devices, the prediction that most IP-based mobile nodes are constantly connected to the wireless networks is fast becoming a reality, Hence, providing mobility support in IP networks has been a long-standing challenge. Although various proposals tried to tackle the Route Optimization (RO) problem, none of them has achieved a satisfactory success. Furthermore, most of them are not a comprehensive solution for coexisting MIPv6 and PMIPv6 mobility environments. In this paper, we focus on challenges to support both MIPv6 and PMIPv6 coexistence from the same wireless access network. This means wireless access network need to support both mechanisms and interaction between them. We first propose a universal IP mobility framework based on a mobility protocol selection method, which takes into account the mobility capabilities of mobile nodes. This allows it to select the most suitable mobility supporting protocol between the MIPv6 and PMIPv6, which can significantly improve the convenience of wireless access network management. Subsequently, in order to reduce the signaling load and handoff latency, we propose a new scheme to reduce the signaling messages of MIPv6 route optimization for support across the MIPv6 and PMIPv6 mobility domains, which can significantly improve the overall performance of mobility management schemes, regardless the mobility environments in which the MNs reside. Simulation results show that proposed framework can improve the performance in terms of the route optimization latency, end-to-end latency, signaling cost, and throughput compared to original MIPv6 route optimization mechanism. Besides, the deployment complexity of both network entities and clients, are expected reduction.

Direct Measurement of Carrier Mobility in Intrinsic Channel Tri-Gate Single Silicon Nanowire Metal–Oxide–Semiconductor Field-Effect Transistors

In this paper, we report the direct measurement of intrinsic carrier mobility in “single”-silicon-nanowire metal–oxide–semiconductor field-effect transistors (MOSFETs) for the first time. To obtain intrinsic carrier mobility with high accuracy by the split capacitance–voltage (C–V) method, ultralong single-silicon-nanowires, instead of multiple parallel nanowires, were designed and fabricated. The open-circuit method was utilized to remove the parasitic effect in measured capacitance. It is found that, although mobility degradations in narrower nanowires are seen in both electrons and holes, the hole mobility is higher than the universal mobility on the (100) surface even in a “single”-nanowire thanks to the high hole mobility on the (110)-oriented side surface of the [110]-directed nanowire. The extracted mobility indicates that surface orientation plays a key role in nanowire mobility.

Metal-Gate/High-$\kappa$/Ge nMOS at Small CET With Higher Mobility Than $\hbox{SiO}_{2}/\hbox{Si}$ at Wide Range Carrier Densities

High-performance TaN/TiLaO/La2O3/SiO2/ (111)-Ge nMOSFETs show high mobility of 432 cm2/V ·s at 1013 cm-2 carrier density (Ns), good 1.05 junction ideality factor, and small subthreshold swing of 101 mV/dec, at a small 1.1-nm capacitance-equivalent thickness (CET). This is the first report of higher mobility in the Ge nMOSFET than SiO2/Si universal mobility at wide medium-high Ns range and small CET of 1.1 nm, which is attributed to using the (111)-Ge substrate, 30-ns laser annealing, SiO2 interfacial layer, and YbGex/n-Ge contact.

Higher Gate Capacitance Ge n-MOSFETs Using Laser Annealing

By applying laser annealing (LA) on both gate dielectrics and source/drain activation, the TaN/ZrO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /La <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> on Ge n-MOSFETs shows a high gate capacitance density, a small n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> /p-junction ideality factor of 1.10, a small subthreshold swing (SS) of 106 mV/dec, and a good high-field mobility of 285 or 340 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V·s after gate leakage correction at 1 MV/cm, at a small 0.95-nm equivalent oxide thickness (EOT). To the best of our knowledge, this is the first demonstration of significantly high gate capacitance in MOSFETs by LA. This is also the highest 1-MV/cm mobility at the smallest EOT of Ge n-MOSFETs and better than the SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Si universal mobility.

Electron Mobility and Short-Channel Device Characteristics of SOI FinFETs With Uniaxially Strained (110) Channels

We have successfully fabricated uniaxially strained SOI (SSOI) FinFETs with high electron mobility and low parasitic resistance. The high electron mobility enhancement on the (110) fin sidewall surfaces was obtained by utilizing effective subband engineering through uniaxial tensile strain along lang110rang, while the substantial reduction of the parasitic resistance was achieved by selective Si epitaxy on the source and drain regions. It was experimentally found that the electron mobility on the (110) sidewall surfaces was significantly enhanced (2.6times) and even surpassed the (100) universal mobility (1.2times). This high mobility enhancement is mainly attributed to the electron repopulation from fourfold valleys having a heavier mass along lang110rang to twofold valleys having a lighter one. In addition, the effective mass reduction of the twofold valleys due to conduction band warping and/or the suppressed surface roughness scattering can also be responsible for the mobility enhancement. Thanks to these high electron mobility enhancement and low parasitic resistance large performance enhancement of 35% was realized in uniaxially SSOI FinFETs with a gate length of 50 nm. This enhancement was evaluated to be as high as ~80% (= 35%/45%) of the intrinsic strain-induced enhancement of the short-channel device performance (45%) at the same strain level (0.8%, ~1.5 GPa) and gate length.

Hole mobility enhancement by double-gate mode in ultrathin-body silicon-on-insulator p-type metal-oxide-semiconductor field-effect transistors

Hole mobility enhancement in double-gate (DG) ultrathin-body (UTB) silicon-on-insulator (SOI) p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) is investigated systematically in comparison with single-gate (SG) UTB MOSFETs for various SOI thicknesses (TSOI) ranging from 2 to 30 nm. It is found that mobility in DG mode (μDG) is higher than that in SG mode (μSG) in all the measured ranges of TSOI and the surface carrier concentrations (Ns). In particular, enhancement of mobility of the sub-10-nm-thick TSOI devices is greater at higher Ns. As a result, it is demonstrated that μDG of the 8.1-nm-thick TSOI device is 12.9% greater than the universal mobility when Ns is 6×1012 cm−2. Higher μDG is attributed to the average effective mass reduction in DG mode because of the increased population in the light hole (LH) bands. Careful investigation also clarifies that mobility in the sub-10-nm-thick TSOI devices is enhanced greatly at higher Ns, since the DG mode-induced increase in the hole population in LH bands is enhanced at higher Ns; the reduction in the hole population in LH bands due to the high-Ns-enhanced carrier confinement in the normal direction is larger in SG mode than in DG mode.

A universal electron mobility model of strained Si MOSFETs based on variational wave functions

A new model is proposed to describe the electron mobility enhancement in strained Si MOSFETs inversion layers using the variational wave functions in the triangular potential approximation. Phonon scattering and surface roughness scattering are included in this model and electron mobility enhancements due to the suppression of these two scatterings are accounted for, respectively. A process-dependent interface parameter is introduced to fit with various technologies. Results from the model show good agreement with experiments for different Ge mole fractions and for a wide range of vertical effective field and temperature. The model is very interesting for implementation in conventional device simulators.

Universal Arrhenius Temperature Activated Charge Transport in Diodes from Disordered Organic Semiconductors

Charge transport models developed for disordered organic semiconductors predict a non-Arrhenius temperature dependence ln(mu) proportional, variant1/T(2) for the mobility mu. We demonstrate that in space-charge limited diodes the hole mobility (micro(h)) of a large variety of organic semiconductors shows a universal Arrhenius temperature dependence micro(h)(T) = micro(0)exp(-Delta/kT) at low fields, due to the presence of extrinsic carriers from the Ohmic contact. The transport in a range of organic semiconductors, with a variation in room temperature mobility of more than 6 orders of magnitude, is characterized by a universal mobility micro(0) of 30-40 cm(2)/V s. As a result, we can predict the full temperature dependence of their charge transport properties with only the mobility at one temperature known.

Tensile-Strained Germanium CMOS Integration on Silicon

Monolithic integration of tensile-strained Si/ Germanium (Ge)-channel n-MOS and tensile-strained Ge p-MOS with ultrathin (equivalent oxide thickness ~14 Aring) HfO2 gate dielectric and TaN gate stack on Si substrate is demonstrated. Defect-free Ge layer (279 nm) grown by ultrahigh vacuum chemical-vapor deposition is achieved using a two-step Ge-growth technique coupled with compliant Si/SiGe buffer layers. The epi-Ge layer experiences tensile strain of up to ~0.67% and exhibits a peak hole mobility of 250 cm2/V ldr s which is 100% higher than the universal Si hole mobility. The gate leakage current is two orders of magnitude lower compared to the reported results on Ge bulk.

Electron mobility and drain current in strained-Si MOSFET

Electron mobility and drain current in a strained-Si MOSFET have been calculated and compared with the mobility and drain current obtained for the relaxed material. In the first step, our mobility model has been calibrated to the “universal mobility” according to the available experimental data for unstrained Si MOSFETS. Then, employing the mobility parameters derived in the calibration process, electron mobility and the drain current have been calculated for strained-Si MOSFETs.

Co-optimization of the metal gate/high-k stack to achieve high-field mobility &gt;90% of SiO/sub 2/ universal mobility with an EOT=/spl sim/1 nm

HfO/sub 2/ and HfSiON gate dielectrics with high-field electron mobility greater than 90% of the SiO/sub 2/ universal mobility and equivalent oxide thickness (EOT) approaching 1 nm are successfully achieved by co-optimizing the metal gate/high-k/bottom interface stack. Besides the thickness of the high-/spl kappa/ dielectrics, the thickness of the ALD TiN metal gate and the formation of the bottom interface also play an important role in scaling EOT and achieving high electron mobility. A phase transformation is observed for aggressively scaled HfO/sub 2/ and HfSiON, which may be responsible for the high mobility and low charge trapping of the optimized HfO/sub 2/ gate stack.

Three-dimensional metal gate-high-/spl kappa/-GOI CMOSFETs on 1-poly-6-metal 0.18-/spl mu/m Si devices

We demonstrate three-dimensional (3-D) self-aligned [IrO/sub 2/-IrO/sub 2/-Hf]-LaAlO/sub 3/-Ge-on-Insulator (GOI) CMOS FETs above 0.18-/spl mu/m Si CMOS FETs for the first time. At an equivalent oxide thickness of 1.4 nm, the 3-D IrO/sub 2/-LaAlO/sub 3/-GOI p-MOSFETs and IrO/sub 2/-Hf-LaAlO/sub 3/-GOI nMOSFETs show high hole and electron mobilities of 234 and 357 cm/sup 2//Vs respectively, without depredating the underneath 0.18-/spl mu/m Si devices. The hole mobility is 2.5 times higher than the universal mobility, at 1 MV/cm effective electric field. These promising results are due to the low-temperature GOI device process, which is well-matched to the low thermal budget requirements of 3-D integration. The high-performance GOI devices and simple 3-D integration process, compatible to current very large-scale integration (VLSI) technology, should be useful for future VLSI.

Characterization of High-κ Nanolaminates of HfO2 and Al2O3 Used as Gate Dielectrics in pMOSFETs

AbstractIn order to combine the merits of both HfO2 and Al2O3 as high-κ gate dielectrics for CMOS technology, high-κ nanolaminate structures in the form of either Al2O3/HfO2/Al2O3 or Al2O3/HfAlOx/Al2O3 were implemented in pMOSFETs and electrically and microstructurally charachterized. ALD TiN film was used as the metal gate electrodes for the pMOSFETs. After full transistor-processing including a rapid thermal processing step at 930 °C, the HfO2 film in the former nanolaminate was found to be crystallized. In contrast, the HfAlOx layer in the latter nanolaminate remained in the amorphous state. Both types of pMOSFETs exhibited a hysteresis as small as ∼20 mV in C-V characteristics in the bias range of +/− 2 V. They also showed a reduced gate leakage current. The pMOSFET with the Al2O3/HfAlOx/Al2O3 nanolaminate was characterized with a subthreshold slope of 77 mV/decade and a channel hole mobility close to the universal hole mobility curve. The pMOSFET with the Al2O3/HfO2/Al2O3, however, exhibited a subthreshold slope of 100 mV/decade and a ∼30% lower hole mobility than the universal curve.

Mobility and performance enhancement in compressively strained SiGe channel PMOSFETs

We report that drive current enhancement and higher mobilities than the universal mobility in compressively strained Si 1− x Ge x on Si surface-channel p-type metal-oxide–semiconductor field-effect-transistors (PMOSFETs) with HfO 2 gate dielectric, for gate lengths ( L G) down to 180 nm. 36% drive current enhancement was achieved for Si 0.8Ge 0.2 channel PMOSFETs compared to Si with HfO 2 gate dielectric. We demonstrate that using SiGe in the channel may be one way to recover the mobility degradation due to the use of HfO 2. Buried-channel PMOSFETs with a Si cap layer and SiO 2 gate dielectrics were also studied. 41% peak mobility enhancement in Si 1− x Ge x channel PMOSFETs was observed compared to Si channel PMOSFETs. 17% drive current enhancement was achieved for 70 nm channel length ( L G) Si 0.9Ge 0.1 PMOSFETs with SiO 2 gate dielectric. This shows the impact of increased hole mobility even for ultra-small geometry of MOSFETs and modest Ge mole fractions. Comparable short channel effects (SCE) were achieved for the buried-channel Si 1− x Ge x devices with L G=70 nm, by controlling Si cap thickness, compared to the Si channel devices. Drive current enhancement without significant SCE and leakage current degradation was observed in this work.

110] strained-SOI n-MOSFETs with higher electron mobility

We have recently developed [110]-surface strained silicon-on-insulator (SOI) n-MOSFETs. The strained-silicon (Si) layer with the strain of about 0.6% has been fabricated on a relaxed SiGe-on-insulator (SGOI) structure with the germanium (Ge) content of 25%. The electron mobility characteristics along the various current directions have been experimentally studied and compared to those of [100]- and [110]-surface unstrained-bulk MOSFETs. We have demonstrated, for the first time, that the electron mobility of [110] strained-SOI MOSFETs is enhanced, compared to that of [110] unstrained-bulk MOSFETs. The electron mobility enhancement depends on the current-flow directions, and the maximum enhancement factor amounts to 23% along the <001> direction. As a result, the electron mobility ratio of [110] strained-SOI MOSFETs to [100] universal mobility is 81% at maximum, whereas the ratio of [110] unstrained-bulk MOSFETs is only 66%. Therefore, [110] strained-SOI devices are also promising candidates for future high-performance CMOS.