United Microelectronics Corporation Research Articles

English

In this paper, first a low-power pulse-triggered flip-flop (FF), a simple two-transistor AND gate is designed to reduce the circuit complexity. Second, a conditional pulse-enhancement technique is devised to speed up the discharge along the critical path only when needed. As a result, transistor sizes in delay inverter and pulse-generation circuit can be reduced for power saving. Various post layout simulation results based on United Microelectronics Corporation and Complementary metal–oxide–semiconductor (UMC CMOS) 50-nm technology reveal that the proposed design features the best power-delay-product performance in several FF designs under comparison. Its maximum power saving against rival designs is up to 18.2% and the average leakage power consumption is also reduced by a factor of 1.52.   Key words: Flip-flop, low power, pulse-triggered, pulse enhancement.

100 mV–1.2 V fully‐integrated DC–DC converters for thermal energy harvesting

Two fully-integrated DC/DC converters for energy harvesting applications are presented. The startup-voltages of the converters are, respectively, 140 and 100 mV, the output voltage exceeds 1.2 V, with a power efficiency of about 20%. The architectures for boosting such extremely low voltages are based on an ultra-low-voltage oscillator cross connected to a capacitive converter. The overall circuits do not require any external components and can be fully integrated in a standard complementary metal oxide semiconductor low-voltage technology. The converters have been designed in United Microelectronics Corporation 180 nm process.

A DC/DC Boosting Technique and Power Management for Ultralow-Voltage Energy Harvesting Applications

With the increasing use of low-voltage portable devices and growing requirements of functionalities embedded into such devices, efficient dc/dc conversion and power management techniques are needed. In this paper, an architecture for boosting extremely low voltages (about 100 mV) to the typical supply voltages of current integrated circuits is presented which is suitable for power harvesting applications too. Starting from a 120-mV supply voltage, the converter reaches an output voltage of 1.2 V, providing an output current of 220 μA and exhibiting a maximum power efficiency of about 30%. Along with the dc/dc converter, a power management circuit is presented, which can regulate the output voltage and improve the overall efficiency. A test chip was fabricated using a United Microelectronics Corporation 180-nm low-threshold CMOS process.

Energy-Efficient FastICA Implementation for Biomedical Signal Separation

This paper presents an energy-efficient fast independent component analysis (FastICA) implementation with an early determination scheme for eight-channel electroencephalogram (EEG) signal separation. The main contributions are as follows: (1) energy-efficient FastICA using the proposed early determination scheme and the corresponding architecture; (2) cost-effective FastICA using the proposed preprocessing unit architecture with one coordinate rotation digital computer-based eigenvalue decomposition processor and the proposed one-unit architecture with the hardware reuse scheme; and (3) low-computation-time FastICA using the four parallel one-units architecture. The resulting power dissipation of the FastICA implementation for eight-channel EEG signal separation is 16.35 mW at 100 MHz at 1.0 V. Compared with the design without early determination, the proposed FastICA architecture implemented in united microelectronics corporation 90 nm 1P9M complementary metal-oxide-semiconductor process with a core area of 1.221 × 1.218 mm2 can achieve average energy reduction by 47.63%. From the post-layout simulation results, the maximum computation time is 0.29 s.

An effective BIST scheme for SRAM full speed test

This article presents a novel built-in self-test (BIST) scheme at full speed test where access time test is performed. Based on normal BIST circuits, we harness an all digital phase locked loop to generate a high-frequency clock for static random access memory (SRAM) performance test at full speed. A delay chain is incorporated to achieve the four-phase clock. As inputs to SRAM, clock, address, data are generated in terms of the four-phase clock. Key performance parameters, such as access time, address setup and hold times, are measured. The test chip has been fabricated by United Microelectronics Corporation 55 nm CMOS logic standard process. According to test results, the maximum test frequency is about 1.3 GHz, and the test precision is about 35 ps at the typical process corner with supply voltage 1.0 V and temperature 25°C.

Evaluation of a Surface-Channel CCD Manufactured in a Pinned Active-Pixel-Sensor CMOS Process

This paper presents measurements on a surface-channel charge-coupled device (CCD) with gates implemented using single-layer poly-silicon gates. The device was manufactured in a 0.18-μm pinned photodiode CMOS process available commercially from the United Microelectronics Corporation. The CCD was built with a field plate covering all gates as well as the space between them, which allows the potential in the gap between nonoverlapping gates to be manipulated. We present charge-transfer-efficiency (CTI) measurements performed at clock frequencies of 1 and 5 MHz, and at multiple background packet sizes and field-plate voltages. We further propose and apply a method for separating CTI in four-phase CCDs due to trapping from the inefficiency stemming from other phenomena. The measurements show a single-stage CTI value ranging from 1.7 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-4</sup> , with a moderate background charge and substantial field-plate voltage, to 0.007 at zero field-plate voltage and the highest background charge tested. The CTI can be reduced significantly (more than a factor of 10 in some cases) by applying a significant negative voltage at the field plate. This and the fact that only a minor part of the CTI can be attributed to trapping indicate that the performance of the device is limited by the presence of potential hollows in the gaps between the gates.

An Inductive Kickback Absorption Scheme Without Power Zener and Large Capacitor

An inductive kickback absorption scheme without a power Zener diode and a large capacitor is presented. Instead of using a power Zener diode and a large capacitor, the proposed scheme uses a control circuit to turn on power transistors available in an H-bridge to save die size, which are used to absorb the kickback energy. Furthermore, the proposed kickback voltage absorption scheme is capable of autoadjusting kickback voltage absorption as changing power supply. The proposed kickback absorption scheme has been realized on a 0.6- United Microelectronics Corporation (UMC) 18-V bipolar/CMOS/DMOS process. The test results demonstrate that the scheme could absorb the inductive kickback voltage rapidly and effectively.

Power-Saving 4 $\times$ 4 Lattice-Reduction Processor for MIMO Detection With Redundancy Checking

In this brief, we propose a lattice-reduction (LR) processor for the LR-aided multiple-input-multiple-output detection. The proposed LR processor was developed based on a modified Lenstra-Lenstra-Lovász (LLL) algorithm. We developed a constant-throughput parallel architecture to realize the real-time operation for the LR. The proposed architecture can detect many redundant operations by checking adjacent parallel LLL-reduction results in the previous stage; thereby, the proposed processor can adaptively reduce the processing power for different channel conditions. We designed and implemented the LR processor using the Virtex-4 field-programmable gate array and the United Microelectronics Corporation 90-nm 1P9M complementary metal-oxide-semiconductor technology. The implementation result shows that the proposed LR processor has the highest throughput compared with that of the previously published works. Moreover, the proposed power-reduction technique can reduce the power by an average of 22.42% or a maximum of 26% with negligible performance degradation.

Algorithm and Architecture of Disparity Estimation With Mini-Census Adaptive Support Weight

High-performance real-time stereo vision system is crucial to various stereo vision applications, such as robotics, autonomous vehicles, multiview video coding, freeview TV, and 3-D video conferencing. In this paper, we proposed a high-performance hardware-friendly disparity estimation algorithm called mini-census adaptive support weight (MCADSW) and also proposed its corresponding real-time very large scale integration (VLSI) architecture. To make the proposed MCADSW algorithm hardware-friendly, we proposed simplification techniques such as using mini-census, removing proximity weight, using YUV color representation, using Manhattan color distance, and using scaled-and-truncate weight approximation. After applied these simplifications, the MCADSW algorithm was not only hardware-friendly, but was also 1.63 times faster. In the corresponding real-time VLSI architecture, we proposed partial column reuse and access reduction with expanded window to significantly reduce the bandwidth requirement. The proposed architecture was implemented using United Microelectronics Corporation (UMC) 90 nm complementary metal-oxide-semiconductor technology and can achieve a disparity estimation frame rate of 42 frames/s for common intermediate format size images when clocked at 95 MHz. The synthesized gate-count and memory size is 563 k and 21.3 kB, respectively.

A Two-Cycle Lock-In Time ADPLL Design Based on a Frequency Estimation Algorithm

This brief presents a frequency estimation algorithm (FEA) for an all-digital phase-locked loop (ADPLL) instead of the traditional binary frequency-searching algorithm. Based on the proposed FEA and a new fast-lock scheme, a fast-lock engine is designed to improve the lock-in time of an ADPLL design with two referenced clock cycles. An implementation of the proposed ADPLL design is realized by utilizing United Microelectronics Corporation (UMC) 0.18-μm 1P6M CMOS technology with a core area of 300 × 250 μm2, consisting of an acceptable input reference clock ranging from 220 kHz to 8 MHz. The ADPLL design has a frequency range of 28-446 MHz with an 8.8-ps digitally controlled oscillator resolution. Moreover, the peak-to-peak jitter of the ADPLL achieves 70 ps, respectively.

A low power cyclic ADC design for a wireless monitoring system for orthopedic implants

This paper presents a low power cyclic analog-to-digital convertor (ADC) design for a wireless monitoring system for orthopedic implants. A two-stage cyclic structure including a single to differential converter, two multiplying DAC functional blocks (MDACs) and some comparators is adopted, which brings moderate speed and moderate resolution with low power consumption. The MDAC is implemented with the common switched capacitor method. The 1.5-bit stage greatly simplifies the design of the comparator. The operational amplifier is carefully optimized both in schematic and layout for low power and offset. The prototype chip has been fabricated in a United Microelectronics Corporation (UMC) 0.18-μm 1P6M CMOS process. The core of the ADC occupies only 0.12 mm2. With a 304.7-Hz input and 4-kHz sampling rate, the measured peak SNDR and SFDR are 47.1 dB and 57.8 dBc respectively and its DNL and INL are 0.27 LSB and 0.3 LSB, respectively. The power consumption of the ADC is only 12.5 μW in normal working mode and less than 150 nW in sleep mode.

Dynamic inhomogeneous S-Boxes design for efficient AES masking mechanisms

It is an important challenge to implement a low- cost power analysis immune advanced encryption standard (AES) circuit. The previous study proves that substitution boxes (S-Boxes) in AES are prone to being attacked, and hard to mask for its non-linear characteristic. Besides, large amounts of circuit resources in chips and power consumption are spent in protecting S-Boxes against power analysis. Thus, a novel power analysis immune scheme is proposed, which divides the data-path of AES into two parts: inhomogeneous S-Boxes instead of fixed S-Boxes are selected randomly to disturb power and logic delay in the non-linear module; at the same time, the general masking strategy is applied in the linear part of AES. This improved AES circuit was synthesized with united microelectronics corporation (UMC) 0.25 μm 1.8 V complementary metal-oxide-semiconductor (CMOS) standard cell library, and correlation power analysis experiments were executed. The results demonstrate that this secure AES implementation has very low hardware cost and can enhance the AES security effectually against power analysis.

On the reverse short‐channel effect and threshold voltage roll‐off controls for 90 nm node MOSFETs

In order to let device designers tune the short channel behavior of MOSFETs, a method is proposed in this work to demonstrate how to use LDD (lightly doped drain) and pocket implants to control RSCE (reverse short channel effect) and threshold voltage (Vt ) roll‐off. The method is based on the process parameters and silicon data of the 90 nm node technology of UMC (United Microelectronics Corporation). With the help of computers, 17 different process conditions of 8 different gate lengths were simulated using ISE TCAD to collect Vt variation data. Four characteristics representing the short channel behaviors of the MOSFETs were designed and extracted from the simulated data. Their empirical equations were also established subsequently. After verification, those mathematical models were demonstrated to help device designers in choosing the most suitable LDD and pocket implant parameters to generate required Vt characteristics.