Abstract
In this paper, first a low-power pulse-triggered flip-flop (FF), a simple two-transistor AND gate is designed to reduce the circuit complexity. Second, a conditional pulse-enhancement technique is devised to speed up the discharge along the critical path only when needed. As a result, transistor sizes in delay inverter and pulse-generation circuit can be reduced for power saving. Various post layout simulation results based on United Microelectronics Corporation and Complementary metal–oxide–semiconductor (UMC CMOS) 50-nm technology reveal that the proposed design features the best power-delay-product performance in several FF designs under comparison. Its maximum power saving against rival designs is up to 18.2% and the average leakage power consumption is also reduced by a factor of 1.52. Key words: Flip-flop, low power, pulse-triggered, pulse enhancement.
Highlights
Flip-flops (FFs) are the basic storage elements used extensively in all kinds of digital designs
It is estimated that the power consumption of the clock system, which consists of clock distribution networks and storage elements, is as high as 20 to 40% of the total system power [Hwang,et el, 2012]
The circuit complexity of a Pulse-triggered FF (PFF) is simplified since only one latch, as opposed two used in conventional master–slave configuration, is needed (Shu, 2006)
Summary
Received 15 August 2013, Accepted 7 July, 2014. First a low-power pulse-triggered flip-flop (FF), a simple two-transistor AND gate is designed to reduce the circuit complexity. A conditional pulse-enhancement technique is devised to speed up the discharge along the critical path only when needed. Transistor sizes in delay inverter and pulse-generation circuit can be reduced for power saving. Various post layout simulation results based on United Microelectronics Corporation and Complementary metal–. Oxide–semiconductor (UMC CMOS) 50-nm technology reveal that the proposed design features the best power-delay-product performance in several FF designs under comparison. Its maximum power saving against rival designs is up to 18.2% and the average leakage power consumption is reduced by a factor of 1.52
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