Unit Gain Frequency Research Articles

Evaluation of n-type gate-all-around vertically-stacked nanosheet FETs from 473 K down to 173 K for analog applications

This work presents an experimental evaluation of n-type, gate-all-around (GAA), vertically stacked nanosheet field effect transistors (NSFETs) operating in a temperature (T) range from 473 K down to 173 K and focusing on their use for analog applications. Devices with gate lengths (Lgate) of 28 nm to 200 nm were analyzed. Besides exhibiting a slight short channel effect, the shorter transistors show a good performance in terms of analog application, presenting at 173 K an intrinsic voltage gain (AV) of 30 dB and unit gain frequency (fT) of 185 GHz. This is also seen in two figures of merit that characterize the transistor performance for analog circuit design: the transistor efficiency (gm/IDS) and the gain frequency product (AV*fT). The optimum region of operation was demonstrated to be at strong inversion by the trade-off between gm/IDS and fT, where in this region Lgate = 28 nm presents a gain frequency product of ∼ 5,5THz at T = 173 K. At lower temperature, as expected, it is confirmed that the carrier mobility and the subthreshold swing (SS) improve while the threshold voltage (VT) increases.

CMOS Wideband Low-Pass Filter Using Complementary Structured OPAMP for Wideband System Applications

In this paper, a CMOS wideband low-pass filter is proposed. In the wide band active filter design, the unit gain frequency (GBW) of OPAMP should be larger than GHz. The GBW of the proposed OPAMP is around 2.3 GHz. Additionally, the OPAMP with a complementary structure in signal and common mode feedback is proposed and has a wide operating voltage range at the input and output. The 1-dB gain compression point (P1dB) at the output is 4.9 dBm. A source follower is employed for driving 50 Ω output impedance without degrading the bandwidth and linearity of the filter. The power consumption is 27 mW from a 1-V supply voltage. The 3 dB bandwidth of the filter ranges from 330 MHz to 660 MHz with 3-bit cap tuning. This work is implemented in a 65-nm CMOS process, with a chip area of 0.18 mm<sup>2</sup>.

Performance Perspective of Gate-All-Around Double Nanosheet CMOS Beyond High-Speed Logic Applications

In this review paper, the performance characteristics of Gate-All-Around (GAA) double nanosheet (NS) MOSFETs are described over a broad temperature range, from 78 K to 473 K (200 oC). Emphasis is on the analog operation, showing good potential. Besides the transistor length, the impact of the metal gate Effective Work Function and the vertical distance between the nanosheets has been studied. Among others, a clear Zero Temperature Coefficient (ZTC) gate voltage has been observed that can be modeled by considering the shift with temperature of the threshold voltage and the maximum transconductance. A trade-off has been noticed between the transistor efficiency and the unit gain frequency, whereby the optimal operation point occurs in strong inversion regime. The feasibility of designing simple analog circuits has also been demonstrated. Finally, a detailed investigation of the low-frequency noise behavior yields good values for the flicker noise Power Spectral Density in comparison with other technology nodes.

Low-voltage Low-power Bulk-driven CMOS Op-Amp Using Negative Miller Compensation for ECG

Two bulk-driven CMOS (Complementary Metal Oxide Semiconductor) operational amplifier (op-amp) designs for electrocardiogram (ECG) application are presented and compared in this paper. Both op-amps are based on two-stage amplification, where bulk-driven differential input is the first stage, while additional DC gain is the second stage. Different compensation techniques were integrated in each op-amp design. Standard Miller compensation was used for the first op-amp parallel with the second stage. The novelty of the second op-amp is that it utilizes negative Miller compensation between the bulk-driven input node and the output node of the first stag, while standard Miller compensation was used in the second stage. The purpose of this work was to compare DC gain, phase margin (PM) and unit gain frequency (UGF) obtained through different simulated compensation strategies and test results. The op-amps were simulated using 0.25 μm CMOS technology. The simulation results are presented using the standard model libraries from Tanner EDA tools, operating on a single rail +0.8V power supply.

Experimental Analysis of Trade-Off Between Transistor Efficiency and Unit Gain Frequency of Nanosheet NMOSFET down to -100 oC

This work presents a trade-off analysis between transistor efficiency (gm/ID which is proportional to the intrinsic voltage gain Av) and the unit gain frequency (fT) of nanosheet (NSH) NMOS devices for temperatures from room temperature down to -100 °C. The analyses were performed experimentally as a function of the inversion coefficient (IC) in order to determine the optimal application region for optimization of both parameters. These analyses were performed with NSH NMOS for channel lengths of 28 nm, 70 nm and 200 nm. It was observed that the optimal operation point takes place in the transition between moderate and strong inversion (IC=10) for the three analyzed temperatures, where the highest value obtained for gm/ID x fT was found. In this optimum bias point the AV is 45 dB (L=200 nm) and 39 dB (L=28 nm) and fT is 9 GHz (L=200 nm) and 186 GHz (L=28nm) both for T=25 °C, which should be suitable for many applications.

Trade-off analysis between gm/ID and fT of nanosheet NMOS transistors with different metal gate stack at high temperature

In this work the gate-all-around nanosheet transistor is analyzed at high temperatures, from analog point of view. At first, the gate-all-around nanosheet (NS) behavior is compared with reported omega-gate nanowire (NW) transistors, at room temperature. It is worth noting that the nanosheets devices present a stronger electrostatic coupling between gate and channel (lower short channel effect -SCE), and higher intrinsic voltage gain, AV (better Early voltage) when compared with NW devices (60 dB for NS and 55 db for NW, with L = 200 nm). Therefore, the second part of this work focuses on the analog study only for NS transistors (with different metal gate stacks), presenting the trade-off between transistor efficiency and unit gain frequency, fT from room temperature to 200 °C. The obtained results are very promising for both gate stack transistors, where values of transistor efficiency about 37 V−1 (T = 25 °C and L = 200 nm) and fT about 260 GHz (T = 25 °C and L = 28 nm) are obtained. The optimal application point was obtained at the transition from moderate to strong inversion.

Air-spacers as analog-performance booster for 5 nm-node N-channel nanosheet transistor

This work investigates the use of air-spacers as an analog-performance booster for nanosheet transistors (NSTs) at 5 nm node. The NSTs with air-spacers are evaluated across the design space for analog circuits. A fully calibrated three-dimensional technology computer-aided design platform was used for the device and mixed-mode circuit simulations. The use of air-spacers improves the output impedance (r o) from 974 kΩ to 1.32 MΩ, as well as the intrinsic gain (A v) from 90 to 118, for the NST with L g/W g = 240 nm/15 nm. The air-spacers also improve analog performance parameters such as the unit-gain frequency (f T) from 562 to 596 GHz; gain-frequency product from 4.76 to 5 THz; transconductance-frequency product from 2.11 to 2.22 THz; and the gain-transconductance-frequency product from 17.9 to 18.7 THz; for the NST with L g/W g value of 12 nm/15 nm. In addition, the discharge time (t d) also improves from 1.64 to 1.5 ns, for NST with L g/W g = 12 nm/120 nm. The oscillation frequency of a three-stage ring-oscillator is also reported to improve from 68.3 to 88.2 GHz by the use of air-spacers.

Impact of ion implantation on stacked oxide cylindrical gate junctionless accumulation mode MOSFET: An electrical and circuit level analysis

This article analyses the effect of ion implantation on electrical and circuit-level characteristics of stacked oxide cylindrical gate (CG) junctionless accumulation mode (JAM) MOSFET. Ion implantation and subsequent annealing create a Gaussian type doping profile inside the channel. A detailed study of electrical characteristics such as: drain current, threshold voltage, Ion/Ioff, transconductance (gm), output conductance (gd), capacitances (Cgs, Cgd, Cgg), unit gain frequency (fT), transit time (τ), transconductance frequency product (TFP) and gain bandwidth (GBW) product have been performed. Further, an inverter has been designed with a complimentary p-MOSFET and a lookup table-based Verilog-A model has been generated for the same. Various dc and transient parameters such as noise margin, rise time, fall time propagation delay, voltage overshoot, average current, and power dispassion have been analyzed in detail. Henceforth, a 6 T SRAM cell has been implemented with ion-implanted stacked oxide CG-JAM MOSFET and read margin, write margin, access time and N-curve analysis have been performed. Various figures of merits (FOMs) have also been studied for the device at the circuit level. All the device simulations have been performed using a 3-D TCAD tool from COGENDA. Verilog-A model-based circuit simulations have been done in the Cadence-Virtuoso platform.

A fully integrated multiphase switched-capacitor DC-DC converter with PFM control and charge sharing loss reduction

A fully integrated high efficiency switched-capacitor (SC) DC-DC converter with pulse frequency modulation (PFM) control is presented. The small signal model of the multiphase-interleaving SC converter is given and it is verified through the simulation and the measurement results. For high efficiency, this design set the dominant pole at the output of the error amplifier (EA) and the 14-phase interleaving topology can push the non-dominant pole away from the Unit Gain Frequency (UGF) for the loop stability. By combining the flying-well and the deep n-well (DNW) isolation techniques, the proposed high-density MOS capacitor can reduce both the parasitic loss and the charge sharing loss of the converter. The conversion ratio of the converter is 2:1 under 3.3V power supply. This SC DC-DC converter is fabricated in the 40 nm CMOS process. It obtains the peak efficiency of 86.2% and the output power-density of 226 mW/mm2. It maintains the efficiency above 80% from 8 mA to 50 mA load condition.

Fin Cross-Section Shape Influence on Short Channel Effects of MuGFETs

Multiple-gate FETs is normally constructed on pre-etched silicon fins. These devices often present casual width variations along the silicon height; mostly caused by technological limitations of the fin definition process, due to non-ideal anisotropic etch. The resulting devices have, consequently, non-rectangular cross-sections, which can affect their electrical behavior. This work addresses the dependence of fin width non-uniformity on the occurrence of short-channel effects through comparative analysis, based on threedimensional numeric simulation of non-rectangular cross-section devices. The influence of the fin crosssection shape on electrical parameters showed to be dependent on channel length, becoming more sensible to the fin shape as the channel length is reduced, with better DC performance present on devices with bottom fin width smaller than top fin width due to the higher transconductance and lower output conductance, resulting on higher intrinsic voltage gain. For opposite fin shapes the total gate capacitance present higher values, beneficiating AC analog parameters, such as unit gain frequency.

Effect of gate length on performance of 5nm node N-channel nano-sheet transistors for analog circuits

In this work, the effect of channel length on the performance of an N-channel Nano-sheet Transistor (NST) for analog circuits has been investigated. A fully-calibrated TCAD platform is used to evaluate the performance of NST devices with channel lengths ranging from 10 nm to 240 nm. The maximum transconductance measured is 0.65 mS for gate length of 24 nm. In addition, the transconductance efficiency ranging from 3 V−1 to 38 V−1 is observed. Intrinsic gain increases from 7.3 to 121.65 as the gate length is varied from 10 nm to 240 nm. For 12 nm gate length, a unit gain frequency of 565 GHz is observed. NST with 24 nm exhibits Gain Frequency Product value of 5.3 THz. The gain-to-power efficiency improvement from 0.048 µA−1 to 2.16 µA−1 is observed. A reversal of relationships of transconductance and other performance parameters with gate length is observed at 24 nm gate length.

Analysis of Omega-Gate Nanowire SOI MOSFET Under Analog Point of View

This paper presents an evaluation of omega-gate nanowire n- and p-type SOI MOSFETs performance focusing on the main analog figures of merit. The different channel widths (WNW) and channel lengths (L) were also evaluated. These devices presented values of subthreshold slope near the theoretical limit at room temperature (60 mV/dec) and in the worst case a DIBL value smaller than 70 mV/V showing its immunity to short channel effects (SCEs) in the range studied. The narrowest device showed great electrostatic coupling, improving transconductance (gm), presenting an unit gain frequency over 200 GHz and intrinsic voltage gain over 80 dB. These values suggests that this device is capable of achieving good performance on new applications such as 5G communications and Internet-of-Things (IoT).

A High-Gain CMOS Operational Amplifier Using Low-Temperature Poly-Si Oxide TFTs

A high-performance CMOS operational amplifier (op-amp) has been demonstrated with the low-temperature poly-Si oxide (LTPO) thin-film transistors (TFTs). The p-type TFT exhibits the maximum field-effect mobility of 80 cm2/V.s and subthreshold swing (SS) of 0.7 V/decade. The n-type amorphous indium–gallium–zinc oxide (a-IGZO) TFT exhibits the SS of 0.3 V/decade and the mobility of 11.5 cm2/V.s. The op-amp consisting of 13 TFTs functions in two stages. It exhibits a high voltage gain of 50.7 dB, a cutoff frequency of 200 kHz, a unit gain frequency of 7 MHz, and a very high gain-bandwidth product of 68.5 MHz. The first LTPO CMOS op-amp with low-power consumption of 0.6 mW demonstrates the potentiality of this emerging technology.

A 0.25-V Rail-to-Rail Three-Stage OTA With an Enhanced DC Gain

This brief proposes a 0.25V rail-to-rail three stage OTA. The proposed OTA improves a DC gain by inserting an NMOS gate-driven amplifier into the conventional bulk-driven OTA. In addition, it uses an asymmetric self-cascode transistor and an indirect feedback compensation to enhance a DC gain and an unit-gain frequency. At the first stage, the bulk-driven amplifier has a rail-to-rail input, but it has a low DC gain due to a small transconductance. At the second stage, the NMOS gate-driven amplifier enhances the DC gain. At the last stage, the common-source amplifier drives an output load capacitor. The proposed OTA was fabricated using a 65nm CMOS process. Its area is 0.002mm2. It consumes $0.026~\mu \text{W}$ at the supply-voltage of 0.25V. The DC gain and unit-gain frequency are 70dB and 9.5kHz, respectively, with the phase margin of 88° at the load capacitance of 15pF.

A High Performance Operational Amplifier Using Coplanar Dual Gate a-IGZO TFTs

We fabricate an operational amplifier (op-amp) composed with the coplanar amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistors (TFTs). The circuit consisted of 19-TFTs and designed on a glass substrate in both dual gate (DG) and single gate (SG) structure for performance evaluation. Having the yield of a total voltage gain ( $A_{v}$ ) of 23.5 dB, a cutoff frequency ( $f_{c}$ ) of 500 kHz, a unit gain frequency ( $f_{\mathrm{ ug}}$ ) of 2.37 MHz, gain-bandwidth product (GBWP) of 7500 kHz, a slew rate (up/down) of (2.1/1.2) V/ $\mu \text{s}$ , and a phase margin (PM) of 102° at a supply voltage of ±10 V, the fabricated DG TFT op-amp demonstrates good performance among all a-IGZO-based literature.

A Solution-Processed Operational Amplifier Using Direct Light-Patterned a-InGaZnO TFTs

In this paper, we present a novel operational amplifier (op-amp) composed with solution-processed n-type amorphous indium-gallium-zinc-oxide (a-InGaZnO) thin-film transistors (TFTs). For patterning a-InGaZnO layer, we used direct light patterning method that drastically reduces the process steps and costs compared to conventional vacuum processes. The a-InGaZnO TFT-based op-amp was designed and fabricated on a glass substrate yielding a total gain of 24.6 dB, a cutoff frequency of 0.47 kHz, and a unit-gain frequency of 2.0 kHz at a supply voltage of ±15 V. Finally, by constituting a pulsewidth modulation controller with the proposed op-amp, we confirmed that the duty ratio and output voltage of the comparator and error amplifier could be altered with respect to the reference voltage, respectively.

Study of the impact of electromigration on integrated circuit performance and reliability at design level

Electromigration damage in interconnects is a well-known bottleneck of integrated circuits, as it is responsible for the performance degradation. High values of temperature and current density accelerate the damage, causing an increase in the lines resistance and circuit lifetime reduction. In this work, a method is proposed to evaluate the electromigration effects in an operational amplifier circuit performance due the void growth induced by electromigration. The performance parameters are simulated by AC, DC and transient analysis for a specific temperature and time interval and the results are compared with a circuit free of electromigration. The method is used to investigate the circuit response regarding the unit gain frequency, voltage gain, cutoff frequency, output swing voltage and settling time. There are three lines that can be traditionally classified as critical due to the large current density they carry. Nevertheless, a fourth line, which has a current density below the maximum limit set by the technology being typically considered as non-critical from the layout design point of view, leads to significant reduction of the voltage gain and voltage swing, of about 59% and 14% in 5years.

Comparative analysis of the intrinsic voltage gain and unit gain frequency between SOI and bulk FinFETs up to high temperatures

This paper presents an experimental analysis of the analog application figures of merit: the intrinsic voltage gain (AV) and unit gain frequency, focusing on the performance comparison between silicon triple gate pFinFET devices, which were processed on both Si and Silicon-On-Insulator (SOI) substrates. The high temperature (from 25°C to 150°C) influence and different channel lengths and fin widths were also taken into account. While the temperature impact on the intrinsic voltage gain (AV) is limited, the unit gain frequency was strongly affected due to the carrier mobility degradation at higher temperatures, for both p- and n-type FinFET structures. In addition, the pFinFETs showed slightly larger AV values compared to the n-type counterparts, whereby the bulk FinFETs presented a higher dispersion than the SOI FinFETs.

A-InGaZnO Thin-Film Transistor-Based Operational Amplifier for an Adaptive DC–DC Converter in Display Driving Systems

In this paper, we present an operational amplifier (op-amp) and a pulsewidth-modulation (PWM) controller fabricated with amorphous indium-gallium-zinc oxide thin-film transistors (a-InGaZnO TFTs), to build an adaptive dc-dc converter for display driving systems. The fabricated a-InGaZnO TFT presents electrical characteristics suitable for accomplishing an op-amp composed only with n-type TFTs to have an overall gain of 24.5 dB, a cutoff frequency of 6 kHz, and a unit gain frequency of 32 kHz operating at ±15 V. The fabricated op-amp is used to construct a comparator and an error amplifier on the glass, which are combined to realize a PWM controller. The resulting PWM controller can successfully control the output voltage of an external dc-dc converter that follows the input voltage to the error amplifier, and can operate at 100 Hz to control the duty ratio from 24.3% to 66.1% when the reference voltage varies from 2 to 6 V, respectively.

Evaluation of Radio-Frequency Performance of Gate-All-Around Ge/GaAs Heterojunction Tunneling Field-Effect Transistor with Hetero-Gate-Dielectric by Mixed-Mode Simulation

In this work, the frequency response of gate-all-around (GAA) Ge/GaAs heterojunction tunneling field-effect transistor (TFET) with hetero-gate-dielectric (HGD) and pnpn channel doping profile has been analysed by technology computer-aided design (TCAD) device-circuit mixed-mode simulations, with comparison studies among ppn, pnpn, and HGD pnpn TFET devices. By recursive tracing of voltage transfer curves (VTCs) of a common-source (CS) amplifier based on the HGD pnpn TFET, the operation point (Q-point) was obtained at <TEX>$V_{DS}=1V$</TEX>, where the maximum available output swing was acquired without waveform distortion. The slope of VTC of the amplifier was 9.21 V/V (19.4 dB), which mainly resulted from the ponderable direct-current (DC) characteristics of HGD pnpn TFET. Along with the DC performances, frequency response with a small-signal voltage of 10 mV has been closely investigated in terms of voltage gain (<TEX>$A_v$</TEX>), unit-gain frequency (<TEX>$f_{unity}$</TEX>), and cut-off frequency (<TEX>$f_T$</TEX>). The Ge/GaAs HGD pnpn TFET demonstrated <TEX>$A_v=19.4dB$</TEX>, <TEX>$f_{unity}=10THz$</TEX>, <TEX>$f_T=0.487$</TEX> THz and <TEX>$f_{max}=18THz$</TEX>.