Unit Gain Frequency Research Articles

VCCS controlled LDO with small on-chip capacitor

A stable LDO using VCCS (voltage control current source) is presented. The LDO is designed and implemented on GF 2P4M 0.35 μm CMOS technology. Compared with a previous compensation scheme, VCCS can implement a real stable LDO with a small on-chip capacitor of 1 pF, whose stability is not affected by the variable ESR (equivalent series resistance) of the output capacitor. The unit gain frequency of the LDO loop can achieve 1.5 MHz, improving the transient response. The PSR of the LDO is larger than 45 dB within 0–40 kHz. The static current of the LDO at heavy load of 100 mA is 57 μA and the dropout voltage of the LDO is 150 mV. Experimental results show that a setting time of 10 μs is achieved, and the variation of output voltage is smaller than 35 mV for a 100 mA load step in transient response of the LDO.

Low Power Operational Transconductance Amplifier (OTA) with Enhanced DC Gain and Slew-Rate

This paper presents a low-voltage differential operational transconductance amplifier (OTA) with enhanced DC gain and slew-rate. Based on the current mirror OTA topology, the optimization techniques are discussed in this work. The proposed structure achieves enhanced DC gain, unit gain frequency (UGF) and slew-rate (SR) with adding four devices. The design of the OTA is described with theory analysis. The OTA operates at the power supply of 1.8V. Simulation results for 0.18μm standard CMOS technology show that the DC gain increases from 60.6dB to 65dB, the UGF is optimized from 2.5MHz to 4.3MHz, the SR is enhanced from 0.88 V/μs to 4.8 V/μs with close power consumption dramatically.

Analysis of the effect of stray capacitance on a charge/discharge-based electrical capacitance tomography system

The measurement circuit of electrical capacitance tomography (ECT) system mainly includes CMOS switches, C/V conversion circuit and Data processing circuit. In order to improve the image reconstruction quality, conversion circuit is very necessary to the small capacitance measurement circuit. A charge/discharge measurement circuit is one of the most suitable for the C/V conversion circuit in ECT. The stray capacitance between the measurement electrodes and earth can be large and have an effect on the capacitance measurement. This paper analyzes this effect, taking into account the ON-resistance of the COMS switch, the unit gain frequency of op-amp, and gain error in the measurement circuit. Finally, it is shown that if the range of stray capacitance is 150±60pF, overall error would be estimated. Comparing the effects of the circuit parameters, this charge/discharge-based capacitance is effectively stray-immune. It is a more efficient analysis to C/V circuit in ECT and offers a great benefit to information processing.

Influence of 45° Substrate Rotation on the Analog Performance of Biaxially Strained Silicon SOI MuGFETs

In this work the influence of the substrate rotation on the analog performance of strained SOI MuGFETs is presented. Measurements performed in fabricated devices show a degradation of the maximum transconductance at both linear and saturation regime. The substrate rotation has no influence on the output conductance. The intrinsic voltage gain and the unit gain frequency were extracted and presented a reduction promoted by substrate rotation, being more evident for a narrow fin.

Influence of 60-MeV Proton-Irradiation on Standard and Strained n- and p-Channel MuGFETs

In this work the proton irradiation influence on Multiple Gate MOSFETs (MuGFETs) performance is investigated. This analysis was performed through basic and analog parameters considering four different splits (unstrained, uniaxial, biaxial, uniaxial+biaxial). Although the influence of radiation is more pronounced for p-channel devices, in pMuGFETs devices, the radiation promotes a higher immunity to the back interface conduction resulting in the analog performance improvement. On the other hand, the proton irradiation results in a degradation of the post-irradiated n-channel transistors behavior. The unit gain frequency showed to be strongly dependent on stress efficiency and the radiation results in an increase of the unit gain frequency for splits with high stress effectiveness for both cases p- and nMuGFETs.

Analysis of temperature variation influence on the analog performance of 45° rotated triple-gate nMuGFETs

This work presents the analog performance of n-type triple-gate MuGFETs with high-k dielectrics and TiN gate material fabricated in 45° rotated SOI substrates comparing their performance with standard MuGFETs fabricated without substrate rotation. Different fin widths are studied for temperatures ranging from 250K up to 400K. The results of transconductance, output conductance, transconductance over drain current ratio, intrinsic voltage gain and unit-gain frequency are studied. It is observed that the substrate rotation improves the carrier mobility of narrow MuGFETs at any temperature because of the changing in the conduction plane at the sidewalls from (110) to (100). For lower temperatures, the improvement of the carrier mobility of rotated MuGFETs is more noticeable as well as the rate of mobility improvement with the temperature decrease is larger. The output conductance is weakly affected by the substrate rotation. Although this improvement in the transconductance of rotated MuGFETs is negligibly transferred to the intrinsic voltage gain, the unity-gain frequency of rotated device is improved due to the larger carrier mobility in the entire range of temperatures studied.

A 1-V Process-Insensitive Current-Scalable Two-Stage Opamp With Enhanced DC Gain and Settling Behavior in 65-nm Digital CMOS

A pseudo-cascode compensation technique is proposed to enable a process-insensitive and current-scalable design of the classical two-stage opamp at low supply voltages, without requiring any additional power dissipation. Furthermore, a bulk-biasing technique is proposed to enhance the dc gain of the two-stage opamp, without affecting its output-voltage swing and without requiring any additional power dissipation. To compare the performance advantages of the proposed pseudo-cascode compensation technique versus classical Miller compensation in a two-stage opamp with/without applying the proposed bulk-biasing technique, four opamps were fabricated on the same die in a 1-V 65-nm CMOS process. The corresponding transistors in all four opamps had equal sizes. Furthermore, all four opamps had equal total compensation capacitance and the same total power dissipation. Accordingly, compared to using Miller compensation, by applying the proposed pseudo-cascode-compensation and bulk-biasing techniques in a two-stage opamp, the opamp's dc gain is increased by a factor of 4 (12 dB), its unit-gain frequency is increased by 40%, and its phase margin is maintained over a factor of 100 scaling in its bias current. Furthermore, the overshoot in its large-signal step response is eliminated and the rise/fall settling times are improved by 33%. The trade-off is a minimal decrease in the opamp's phase margin. Importantly, this is all achieved without affecting the opamp's output-voltage swing and without requiring any additional power dissipation.

An ultra-low-power CMOS symmetrical OTA for low-frequency G m -C applications

In this paper an ultra-low-power CMOS symmetrical operational transconductance amplifier (OTA) for low-frequency G m -C applications in weak inversion is presented. Its common mode input range and its linear input range can be made large using DC shifting and bulk-driven differential pair configuration (without using complex approaches). The symmetrical OTA was successfully verified in a standard CMOS 0.35-μm process. The measurements show an open loop gain of 61 dB and a unit gain frequency of 195 Hz with only 800 mV of power supply voltage and just 40 nW of power consumption. The transconductance is 66 nS, which is suitable for low-frequency G m -C applications.

A low noise compact class AB buffer amplifier with accurate quiescent current control

The authors present a new low-noise class AB buffer amplifier. The proposed buffer amplifier achieves a low noise with fast settling time and low power consumption. The buffer amplifier circuit attains an input referred noise voltage of 12.8 $$ {{\text{nV}} /{\sqrt {\text{Hz}}}} $$ , a DC gain of 108 dB, a unit-gain frequency of 8 MHz, and rising slew rate of 36 V/μs, as the load capacitance equals 150 pF. The circuit is power efficient when driving large capacitive loads and is well suited for low noise low power analog video buffer applications.

A CMOS 90 nm 55 mW 3.4-to-9.2 GHz 12 Band Frequency Synthesizer for MB-OFDM UWB

A frequency synthesizer for ultra-wideband (UWB) multiband orthogonal frequency division multiplexing (MB-OFDM) applications is designed in TSMC 90 nm CMOS technology. It is based on two wideband PLLs (8 MHz open loop unit gain frequency) capable of settling in less than 300 ns with a 66 MHz external reference. The PLL tuning range (6.6-9.2 GHz) is extended down to 3.4 GHz by a dedicated circuit able to divide the output frequency by 1, 1.5 and 2 with a power consumption of less than 3 mW. Measured data fit the UWB MB-OFDM specifications with an integrated phase noise of 2.8RMS o at maximum output frequency and an aggregate spurious tone power of less than -27 dBc. The joint power consumption is 55 mW and the synthesizer core area occupies less than 0.5 mm2 .

Trapezoidal SOI FinFET analog parameters' dependence on cross-section shape

The trapezium is often a better approximation for the FinFET cross-section shape, rather than the design-intended rectangle. The frequent width variations along the vertical direction, caused by the etching process that is used for fin definition, may imply in inclined sidewalls and the inclination angles can vary in a significant range. These geometric variations may cause some important changes in the device electrical characteristics. This work analyzes the influence of the FinFET sidewall inclination angle on some relevant parameters for analog design, such as threshold voltage, output conductance, transconductance, intrinsic voltage gain (AV), gate capacitance and unit-gain frequency, through 3D numeric simulation. The intrinsic gain is affected by alterations in transconductance and output conductance. The results show that both parameters depend on the shape, but in different ways. Transconductance depends mainly on the sidewall inclination angle and the fixed average fin width, whereas the output conductance depends mainly on the average fin width and is weakly dependent on the sidewall inclination angle. The simulation results also show that higher voltage gains are obtained for smaller average fin widths with inclination angles that correspond to inverted trapeziums, i.e. for shapes where the channel width is larger at the top than at the transistor base because of the higher attained transconductance. When the channel top is thinner than the base, the transconductance degradation affects the intrinsic voltage gain. The total gate capacitances also present behavior dependent on the sidewall angle, with higher values for inverted trapezium shapes and, as a consequence, lower unit-gain frequencies.

Gain improvement in operational transconductance amplifiers using Graded-Channel SOI nMOSFETS

This paper studies the performance of operational transconductance amplifiers (OTAs) fabricated with Graded-Channel (GC) SOI nMOSFETs and designed to provide high open-loop voltage gain or high gain-bandwidth characteristics. Different design targets were taken in account such as similar power dissipation, transconductance over drain current ratio and die area. Comparisons with OTAs made with conventional SOI nMOSFETs, are performed showing that the GC OTAs presents larger open-loop voltage gain without degrading the phase margin, unit gain frequency and slew rate simultaneously with a significant required die area reduction depending on LLD/L ratio used. Circuit simulations and experimental results are used to qualify the analysis.

Improvement on frequency characteristics of integrator-based filters by reducing spread of unity-gain frequencies

ln the design of integrator-based filters, there are degrees of freedom in selection of the signal flow graph representing the connection state of the integrator. In this paper, a procedure is proposed for selecting the signal flow graph for a filter with a small deviation from the ideal frequency characteristics. In general, the integrator works ideally near the unit-gain frequency. Hence, in order to realize a filter with excellent characteristics, a guideline is described for selecting the signal flow graph such that the unit-gain frequencies of all integrators used in the filter are close to each other. Since the amount of computation for selection of the signal flow graph becomes enormous even in a filter of low order, an evaluation scale for search is used that can easily estimate the spread of the unit-gain frequencies in individual signal flow graphs. As examples, the signal flow graphs are derived for the fifth-order maximally flat-delay low-pass filter and the third-order amplitude equal-ripple low-pass filter. The validity of the proposed evaluation scale is presented. The effectiveness of the design guideline is confirmed by a computer simulation of the filter made up of MOSFET based on the obtained signal flow graphs. © 2000 Scripta Technica, Electron Comm Jpn Pt 3, 83(6): 61–68, 2000