Wafer Uniformity Research Articles

Effect of GaN Substrate Properties on Vertical GaN PiN Diode Electrical Performance

Present GaN technology consists primarily of heteroepitaxial, lateral high electron mobility transistors; however, high-power devices would be much more efficiently manufactured with a vertical geometry due to better blocking voltage scaling. This technology has yet to be realized due to the inconsistency of GaN wafer properties. These inconsistencies can be detected with several long-range, non-destructive techniques including Raman spectroscopy, optical profilometry, and photoluminescence mapping. In particular, Raman spectroscopy is an effective tool for determining the carrier concentration of GaN substrates and whether the wafers are uniform or inhomogeneous. In this work, vertical p-i-n GaN diodes are fabricated using both uniform and inhomogeneous wafers determined by using the A1 Raman peak position to monitor carrier concentration. The inhomogeneous samples have regular patterns of varying conductivity as a result of electron-donating defects brought about by changes in crystal stress. By avoiding these defects, we have found that diode performance improves by increasing the +/− 10 V rectification ratio by up to a factor of 5X and reducing the 200 V reverse bias leakage current by several orders of magnitude. Using the higher quality substrates with uniform electron carrier concentrations can improve the rectification ratio by another order of magnitude.

Study on Uniform Deposition on 300 mm Silicon Wafer with Sub-100 nm Sized Particles for Cleaning Application

A study for uniform deposition on whole area of wafer was conducted to help check the uniformity of cleaning technology between wafer center to edge. A new method of particle deposition was devised different from the conventional studies using the center nozzle and electric field. Our deposition chamber features wafer rotating method and deposition by the principle of convection and diffusion. In this study, we focused on the effect of wafer rotation speed and rotation number to particle deposition result. After setting the optimum condition, fine results with well deposited shape on whole area of the wafer and outstanding particle size uniformity of more than 70% were obtained. Although particle size shift phenomenon occurred in the measurement result using SP5 due to the intrinsic principle, SEM analysis demonstrated that particles with 60, 80 nm sized silica particles were well deposited on wafer. We believe the standard wafer made by our particle deposition system could be utilized and helpful for performance evaluation and development of wafer cleaning technologies.

Pre-Texturing Thermal Treatment for Saw-Damage-Removal-Free Wet Texturing of Monocrystalline Silicon Wafers

The etching of Si wafers significantly influences the efficiency of photovoltaic devices. Texturing can effectively decrease front surface reflection and improve device performance. Saw damage removal (SDR) is necessary to yields uniform random pyramidal surfaces without the appearance of saw marks, it entails significant consumption of chemical solutions and complicated cleaning steps. Herein, an alternative process of pre-texturing thermal treatment was carried out at 800 °C for 10 min, followed by anisotropic texturing, and a uniform pyramidal surface over a large area of the textured surface was obtained without saw marks. Compared with that of as-cut mono-Si wafers (30.7%), the weighted average reflectance of the samples textured with or without thermal treatment decreased to 11.2% and 11.9%, respectively, and further to 3% and 3.4%, respectively, when anti-reflection coatings were applied. In addition, saw marks on the wafer surface were used as gettering sites during thermal treatment, and the bulk lifetime was more than doubled from 42.6 µs before the treatment to 93.8 µs after. The simple, SDR-free method presented herein for enhancing the textural uniformity of Si wafers and, hence, solar cell performance, can be employed on an industrial scale without necessitating additional investment in equipment.

Epitaxial Growth of Active Si on Top of SiGe Etch Stop Layer in View of 3D Device Integration

Three-dimensional System-On-Chip (3D-SoC) technology schemes require wafer-to-wafer bonding combined with good control of the Si thickness and the Si within wafer uniformity [1,2]. As a result, there is a renewed interest in epitaxial strained Si1-xGex as etch stop layer [3]. Epitaxial growth by means of Chemical Vapor Deposition (CVD) offers excellent control of layer thickness and material composition. If needed, the Si cap layer can be in-situ doped. The challenge is to develop low cost epitaxial growth processes without compromising the material quality. Indeed, relaxation of the Si1-xGex layer must be avoided as the presence of threading dislocations in the Si-cap has a detrimental effect on electrical properties and the yield of the devices fabricated afterwards. On the other hand, the Ge concentration in the Si1-xGex layer should be sufficiently high to guarantee etch selectivity with respect to the underlying Si substrate [4]. The Si1-xGex layer also needs to be relatively thick as some material loss cannot be avoided. Etching of the Si-cap layer during wafer back-side thinning must be prevented.In this contribution, we discuss the different challenges for the epitaxial growth of such Si-cap / Si1-xGex // Si-substrate layer stacks, with Si-cap layer thicknesses ranging from 20 to 500 nm and a targeted Ge content in the Si1-xGex layer of 25%. All epi-layers discussed in this work were grown in an ASM Intrepid RP-CVD cluster tool, aiming the highest possible process throughput. To control the epitaxial material quality, fast and reliable in-line metrology and inspection techniques are required. For instance, Wostyn et al. recently reported on inline light scattering measurements, commonly used to determine wafer quality and cleanliness, and have shown that the technique is also suitable to study the crystalline quality after hetero epitaxy [5].Standard deviations in thickness below 1.5% as measured for both the Si0.74Ge0.26 and the Si-cap layers by means of Spectroscopic Ellipsometry illustrate the within wafer uniformity of the epitaxially grown layer stacks. The Si0.74Ge0.26 material quality is confirmed by the presence of well-defined Kiessig fringes on the (004) XRD spectrum. The lack of a surface crosshatch pattern in AFM and the very low haze values as obtained from light scattering measurements using the KLA Surfscan® SP3 indicate the absence of misfit dislocations in uncapped Si0.74Ge0.26 layers for thicknesses up to 100 nm. After Si capping, RSM measurements still indicate that the layer is fully strained (Fig. 1a). Moreover, no defects were detected by commercial in-line defect inspection systems such as the KLA Electron-Beam Wafer Defect Review (EDRT M) System and the automated optical inspection system. However, depending on the process conditions, enhanced haze values might be measured. This enhanced surface roughness is due to the presence of misfit dislocations as evidenced by AFM (Fig. 1b). A careful process optimization enables the deposition of Si-cap / Si0.75Ge0.25 // Si-substrate bilayers with low haze values which are completely free of misfit dislocations, still allowing a Si-cap thickness of up to 500 nm and a relative high processing throughput (Fig. 1d). Still, it is striking that in case of 300 mm substrates, layer relaxation, if present, starts at the edge of the wafer (Fig. 1c) [6]. Therefore, special care needs to be taken to ensure that no relaxation is initiated at wafer edges. Extremely sensitive characterization methods are mandatory to detect the onset of relaxation and to ensure the fabrication of defect-free epi stacks. The developed epi process was successfully implemented in 3D device integration schemes to fabricate stacked Gate All Around devices and to demonstrate functional backside integration.

Sub-surface Damage of Ultra-Thin Monocrystalline Silicon Wafer Induced by Dry Polishing

Ultra-thin wafer fabrication has become a hot spot in recent years with the growing demand for small size and high performance electronic devices. However, far less research focused on the damage behavior in ultra-thin wafer. In this work, 300 mm diameter silicon wafer was thinned to 6 µm thick by grinding plus ultra-precision dry polishing. The damage behavior before and after the dry polishing was discussed. Mechanical and surface analysis showed that the dry polishing process can help improve the strength and surface uniformity of ultra-thin wafer by removing high pressure phase and micro cracks. Series of nano beam diffraction patterns revealed the stress induced by the thinning process only existed in surface. High resolution transmission electron microscopy images analyzed by geometric phase approach indicated that surface dislocations can move across the wafer and reached bottom device layers during the dry polishing, increasing the risk of electrical deterioration. The findings are of great significance to the study on process optimization of ultra-thin wafer and provide insights into the reliability of advanced electronic packaging.

(Keynote) Low Temperature SmartCutTM Process for 3D Integration

— To support 3D Sequential integration with a cost-effective layer transfer, SmartCut™ process at low temperature (below 500 °C) is proposed. Excellent SOI & BOX layer thickness uniformities are demonstrated, while layer integrity, electron and hole mobility performances are already compliant with development grade requirements. Keywords—SmartCut, 3D Integration, Low Temperature, CMOS I. SmartCut Proposal for 3D Sequential IntegrationIn support of the semiconductor evolution, 3D integration is considered, addressing several challenges: integration of multiple types of devices including specialized components, continuous footprint reduction as well as optimization of performance and cost [1]. However, a key challenge for 3D integration, shown on Figure 1 reported in reference [2], is the preparation of a top tier device using as handle surface a fully processed bottom tier device. Hence, the top tier device thermal budget needs to be reduced to avoid degradation of the bottom devices [3]. A mandatory 500 °C thermal budget limitation for 3D Sequential Top layer transfer and MOSFET fabrication is then considered [2, 4].In order to take advantage of the SmartCut process to transfer at reduced cost (i.e. avoiding a conventional but costly SOI bonding & grinding process) a high quality, highly uniform crystalline layer, we propose the use of a new Low Temperature SmartCut process as an alternative for 3D integration. This paper reports on our findings from such transfer demonstrations on bare handle materials, including for the first time SOI-like layer electrical characterization results.II. Low Temperature SmartCut for 3D IntegrationFor 3D integration, SmartCut process is adapted as schematically shown on Figure 2 in order to transfer at low temperature ultra-thin layers compatible with fully depleted requirements. This process option includes the use of engineered, epitaxial processed donor wafers. The epitaxial process on conventional bulk material allows creation of a first Silicon-Germanium layer, to be used as an etch stop layer after SmartCut splitting. Then a subsequent Si layer, defined accordingly to the SOI film thickness target, is epitaxied. Implant, surface preparation, bonding, splitting process steps, all being compliant with maximum 500 °C low temperature requirement, benefit from conventional FD-SOI experience. Finishing process includes selective etching to recover SOI layer [5]. Then a dedicated curing process step is considered in order to optimize SOI layer electrical properties. Silicon Phase Epitaxial Regrowth (SPER) as described in reference [6] is proposed.Figure 3 highlights such low temperature layer transfer process on a patterned handle wafer. Picture is obtained after SmartCut splitting process step. A visual defect free layer is obtained.III. Low Temperature SOI Performance on Bare Handle waferThe SOI layer thickness variability, over the full spatial wavelength spectrum from device to wafer scale, is driven by the donor epitaxy performance. Figure 4 shows Atomic Force Microscopy (AFM) roughness performance, through 30x30 µm² scan. RMS of 1.0 and 0.9 Å are measured on high and low temperature process options respectively. Best in class performance is then obtained thanks to Low Temperature SmartCut.Figure 5 shows (a) BOX and (b) SOI layers ellipsometry thickness mapping, on a 12 nm SOI / 20 nm BOX sample. BOX layer variability is primarily driven by thermal oxide growth, thus demonstrating a within wafer uniformity << 10 A. SOI layer thickness variability is mainly driven by epitaxy performance on the engineered donor wafer.Figure 6 shows typical KLA Tencor SP3 @ 65 nm threshold defect mapping, as measured on 12 / 20 nm low temperature R&D sample. Micro-defect density on this early development product already demonstrates less than 0.1 defect / cm² performance.Then Figure 7 compares PsiMOS measured electron and hole mobility in the SOI layer using High and Low Temperature SmartCut processes. A as low as 10% mobility performance difference between both processes vintage is already demonstrated.IV. ConclusionTo support 3D sequential integration, layer transfer at low temperature (< 500 °C) is demonstrated thanks to an adapted SmartCut process. Next research step will confirm this capability with low temperature layer transfer on patterned substrate for 3DS device assessment.V.

X-ray diffraction and Raman characterization of β-Ga2O3 single crystal grown by edge-defined film-fed growth method

The crystallinity and wafer uniformity of (2¯01) and (010) oriented β-Ga2O3 substrates grown by edge-defined film-fed growth (EFG) were investigated by laboratory X-ray diffraction (XRD), synchrotron XRD, polarized Raman spectroscopy, and Raman mapping. XRD results indicated that the EFG substrates had superior crystallinity and high uniformity. Position-dependent XRD ω-rocking curves recorded across a 50.8-mm-diameter substrate had small standard deviations of δF = 1.6% for the full width at half maximum and δP = 2.8% for the peak intensity. The radius of curvature was measured to be 37.7 m for the (2¯01) substrate and 16.4 m for the (010) substrate. The results of synchrotron XRD with various beam sizes suggested that the curving of crystal planes was mainly along the [010] growth direction rather than along the [102] direction. Raman spectra showed that Sn doping up to 3.3 × 1018 cm−3 did not give rise to a notable Raman peak shift. The strain distribution evaluated by Raman mapping implied the high uniformity of both (2¯01) and (010) substrates. From these results, it was concluded that β-Ga2O3 ingots grown by EFG have high crystallinity and can be treated as three-dimensionally uniform bulk crystals in the cases of both undoped and Sn-doped growth.

Investigation of the distribution of deep levels in 4H-SiC epitaxial wafer by DLTS with the method of decussate sampling

• Z 1/2 defect typically exist in n-type 4H-SiC epitaxial layer. • Defect concentration uniformity of the epilayer is 5.74%. • Z 1/2 defect is uniformly distributed in 4-inch n-type 4H-SiC epitaxial layer. • Ti center did not appear at the temperature range from 80 K to 500 K. In this paper, Schottky structures were fabricated on the epitaxial wafers and the deep levels of the wafers were measured by deep level transient spectroscopy (DLTS). The thickness of the commercial n-type 4°off-axis 4H-SiC (0 0 0 1) epitaxial wafers was 100 μm, with a doping concentration of 2 × 10 14 cm −3 . Nine sample points were selected along with the direction of [1–100] and [11–20] on the wafer. Through the peak fitting analysis of the test results, the detailed information of deep level defects in the epitaxial layer was obtained. The typical deep level defect Z 1/2 was found, but Ti center did not appear, which indicates that Ti center was not introduced in our technological process. Defect concentration uniformity of the 4-inch 4H-SiC epitaxial wafer is 5.74%. The results demonstrate that although the concentration of Z 1/2 defect differs in different locations, but the difference is so small that Z 1/2 defect concentration can be considered to be evenly distributed across the wafer.

Multi-staged deposition of trench-gate oxides for power MOSFETs

Here, silicon oxide was formed in a U-shaped trench of a power metal-oxide semiconductor field-effect transistor device by various processes. One SiO2 formation process was performed in multiple steps to create a low-defect Si-SiO2 interface, where first a thin initial oxide was grown by thermal oxidation followed by the deposition of a much thicker oxide layer by chemical vapor deposition (CVD). In a second novel approach, silicon nitride CVD was combined with radical oxidation to form silicon oxide in a stepwise sequence. The resulting stack of silicon oxide films was then annealed at temperatures between 1000 and 1100 °C. All processes were executed in an industrial environment using 200 mm-diameter (100)-oriented silicon wafers. The goal was to optimize the trade-off between wafer uniformity and conformality of the trenches. The thickness of the resulting silicon oxide films was determined by ellipsometry of the wafer surface and by scanning electron microscopy of the trench cross sections. The insulation properties such as gate leakage and electrical breakdown were characterized by current–voltage profiling. The electrical breakdown was found to be highest for films treated with rapid thermal processing. The films fabricated via the introduced sequential process exhibited a breakdown behavior comparable to films deposited by the common low-pressure CVD technique, while the leakage current at electric fields higher than 5 MV/cm was significantly lower.

A Material Removal Rate Model for Tungsten Chemical Mechanical Planarization

In this work, a new material removal rate (MRR) model for tungsten chemical mechanical planarization (CMP) is proposed to provide some fundamental insights of slurry components and contact behavior on the removal mechanism. The synergistic effect of mechanical abrasion and chemical reactions on MRR is systematically investigated through using concepts of the steady-state equilibrium, chemical growth kinetics and contact mechanics in W CMP process. A closed-form equation of MRR is formulated to capture the influence of the slurry chemistry and operating parameters on the surface removal mechanism. Then the tungsten CMP model is simplified and verified through comparing the simulated results of removal rates with experimental data. It is found that the MRR has complicated variation behaviors depending on the specific model parameters. The consistency of the simulation results and experiments indicates that the present model can be adopted to capture the influences of chemicals, mechanical abrasion and pad properties on the polishing rate and assist in optimizing the surface uniformity of tungsten wafers.

Investigation of the effect of chemical pre-treatment on uniformity of the silicon wafer texturing for manufacturing a solar cell

The role of chemical pre-treatment on silicon surface quality and texturing uniformity was investigated. It was shown that for better uniformity of texturing the initial silicon surface of as-cut slurry sawed wafer should be treated to clean up from organic and metal contaminations followed by the organic solvent traces removing and saw damaged silicon layer etching. Additional measurements of photoluminescence decay confirmed high quality and uniformity of textured wafers passivated by a-Si:H.

Observer-based temperature control of an LED heated silicon wafer

The key issue in semiconductor rapid thermal processing (RTP), where silicon wafers are heated to desired temperatures, is to ensure uniform wafer temperature profiles. This in turn guarantees that the manufactured integrated circuits (IC), which are spread over the entire wafer, can be processed in an equal measure. In this study, a mathematical model capturing the physical behavior of the heating-up process is presented. It relies mainly on the well-known partial differential heat equation, governing the temperature distribution in a given region of a given material. Based on this, an observer as also a control law is proposed, which in combination turned out to be superior to conventional RTP strategies. The approach is validated in practice at a real world heating system with different wafer types.

Wafer Level Variability Improvement by Spatial Source/Drain Activation and Ion Implantation Super Scan for FinFET Technology

In this paper, CMOS wafer level ring oscillator frequency variability improvement >40% is demonstrated by either spatial source/drain activation or ion implantation super scan in FinFET technology. Yield improvement (up to 17%) is verified with better within wafer uniformity and with no intrinsic device performance degradation. Furthermore, the combination of super scan and spatial source/drain activation is suggested for optimized variability improvement benefits from individual device type uniformity tuning (super scan) and all device type uniformity tuning (from spatial S/D activation).

Effect of Large Particles During Chemical Mechanical Polishing Based on Numerical Modeling of Abrasive Particle Trajectories and Material Removal Non-Uniformity

A numerical simulation that describes particle trajectories during chemical mechanical polishing by Zhao et al. was extended to account for the effects of larger particles in a slurry, particle location changes due to slurry dispensing and in-situ conditioning. Material removal rate (MRR) and within wafer non-uniformity were determined based on the calculated particle trajectory densities in the absence of chemical activity from the slurry and assuming that the pressure is uniform and constant. The effect of pad-wafer rotary dynamics and reciprocating motion of the wafer carrier on MRR uniformity were evaluated and typically edge-fast MRR profiles were obtained. It was also shown that in-situ conditioning improves the MRR uniformity of the polished wafers. Using the model, we also investigated the effect of particle size distribution and large particles (>200 nm in diameter) on wafer uniformity and scratch growth and compared with some of our wafer level defect data. It was shown that the presence of even 1 wt.% of larger particles can deteriorate the wafer uniformity.

High-uniformity centimeter-wide Si etching method for MEMS devices with large opening elements

We propose a compensated mesh pattern filling method to achieve highly uniform wafer depth etching (over hundreds of microns) with a large-area opening (over centimeter). The mesh opening diameter is gradually changed between the center and the edge of a large etching area. Using such a design, the etching depth distribution depending on sidewall distance (known as the local loading effect) inversely compensates for the over-centimeter-scale etching depth distribution, known as the global or within-die(chip)-scale loading effect. Only a single DRIE with test structure patterns provides a micro-electromechanical systems (MEMS) designer with the etched depth dependence on the mesh opening size as well as on the distance from the chip edge, and the designer only has to set the opening size so as to obtain a uniform etching depth over the entire chip. This method is useful when process optimization cannot be performed, such as in the cases of using standard conditions for a foundry service and of short turn-around-time prototyping. To demonstrate, a large MEMS mirror that needed over 1 cm2 of backside etching was successfully fabricated using as-is-provided DRIE conditions.

Room-temperature direct bonding of silicon and quartz glass wafers

We demonstrate a facile bonding method for combining Si/Si, Si/quartz, and quartz/quartz wafers at room temperature (∼25 °C) using a one-step O2/CF4/H2O plasma treatment. The bonding strengths were significantly improved by adding a small amount of CF4 into the oxygen plasma, such that reliable and tight bonding was obtained after storage in ambient air for 24 h, even without employing heat. Moreover, by introducing water vapor during O2/CF4 plasma treatment, uniform wafer bonding was spontaneously achieved without applying an external force. The fluorinated surface asperities appear to be softened more easily by the interfacial water stress corrosion, enabling reliable bonding at room temperature. Additionally, adding an optimized amount of water vapor to the O2/CF4 plasma increases sufficiently the amount of hydroxyl groups without eliminating the CF4 effect. The additional water adsorbed on the surface may help to close the gap between the bonded wafers, resulting in better bonding efficiency.

Optimization of Phosphorus Emitter Formation from POCl3 Diffusion for p-Type Silicon Solar Cells Processing

The main purpose of this work is to demonstrate the possibility of diffusion process perfection during silicon solar cells manufacturing by CFD simulation. Presently, the major community of PV industries uses a p-type silicon solar cell as the starting material. In this work too, boron doped silicon wafers are considered to form solar cells. Likewise, phosphorus oxy-chloride (POCl3) is used as a precursor for phosphorus diffusion. To do this, we evaluate the throughput of an industrial low-pressure diffusion tube furnace in order to realize uniform emitters. The low-pressure tube furnace is designed to obtain emitter standard sheet resistances of about 60 Ω/sq and wafer uniformity less than 3 %. An up-to-date control model using for the first time a CFD numerical code has been derived from some previous work, to achieve better wafer to wafer temperature distribution. Moreover, a numerical process was built using an Atlas-Silvaco® TCAD Simulation Package where we can demonstrate that the short circuit current density (Isc) increases from 4.97 to 6.53 mA/cm2 compared to the conventional photovoltaic process. This (Isc) enhancement can be attributed to the strong temperature effect on furnace atmosphere. Our result proves that we can target electrical properties of an emitter only by the manipulation and optimization of the doping profile. This process refinement is expected to contribute in the development of high efficiency conventional crystalline silicon solar cells considered for mass production.

Advanced Process Control for Variability Control in Chemical Mechanical Polishing Process

With semiconductor technologies driving towards sub 14nm nodes, FIN based field effect transistors (FINFETs) have been the preferred design to meet device power and performance requirements. At the core of FINFET transistor design is gate last/replacement metal gate (RMG) integration scheme due to the advantages in thermal budgets. Chemical mechanical planarization has evolved from planarization technique to technology enabler for this integration scheme. Replacement metal scheme has its own share of challenges- the integration scheme is quite complex. Chemical mechanical planarization (CMP) plays a key role in enabling this integration with various CMP steps supporting dummy poly gate formation, poly removal and replacement metal gate formation. The final gate height of the replacement metal gate is one of the most important parameters controlling device resistance. Even a change of 1nm gate height can result in overall variation of 5ohms/sq resistance. This requires CMP to control gate height as tightly as possible for every wafer. The two important factors contributing to the overall gate height variation are upstream processes and the metal gate CMP process itself. It is well known that CMP has its own variability in removal rate depending on consumable life resulting in unstable gate height. The gate height variation needs to be controlled within wafer and every wafer. A dedicated metrology tool connected to the polishing tool has been employed for many years to measure wafer thickness parameters. This onboard metrology tool is used to measure every wafer and the data is used to develop automated process control to improve overall within wafer and wafer to wafer variation. A two fold approach is used to achieve this. Integrated automated process control (iAPC) is initially used to control wafer to wafer variation and furthermore, zonal integration automated process control is used to improve within wafer uniformity. The basic concept is to use metrology data collected from each wafer and create a model to adjust polishing time to achieve desired final gate height target. Using these two approaches, gate height control of less than 5nm has been demonstrated consistently. Both these approaches will be discussed in detail.

An experimental investigation of flat polishing with dielectrophoretic (DEP) effect of slurry

Dielectrophoresis polishing (DEPP) is a novel flat polishing technology which utilizes the dielectrophoretic (DEP) effect to reduce the centrifugal force on the slurry and to obtain a higher polishing efficiency. The mechanism of the DEPP was analyzed in this paper; the motion of slurry being acted upon by DEP force in non-uniform electric field was captured in real-time with a specially designed video recording system to show the influence of electric field intensity and frequency upon DEP force. DEPP and traditional CMP were investigated. These processes were carried out in sequence on the same machine with the same slurry. Compared with traditional CMP, the efficiency of DEPP was improved by about onefold and the better surface uniformity of silicon wafer was obtained. The final surface roughness Ra of silicon wafer was measured at 1.2 nm.

Photoluminescence Characterisation of High Current Density Resonant Tunnelling Diodes for Terahertz Applications

High structural perfection, wafer uniformity, and reproducibility are key parameters for high-volume, low cost manufacture of resonant tunnelling diode (RTD) terahertz (THz) devices. Low-cost, rapid, and non-destructive techniques are required for the development of such devices. In this paper, we report photoluminescence (PL) spectroscopy as a non-destructive characterisation technique for high current density InGaAs/AlAs/InP RTD structures grown by metal-organic vapour phase epitaxy (MOVPE) for THz applications. By using a PL line scanning technique across the edge of the sample, we identify characteristic luminescence from the quantum well (QW) and the undoped/n InGaAs layers. By using the Moss-Burstein effect, we are able to measure the free-electron concentration of the emitter/collector and contact layers in the RTD structure. Whilst the n InGaAs luminescence provides information on the doping concentration, information on the alloy composition and compositional variation is extracted from the InGaAs buffer layer. The QW luminescence provides information on the average well width and provides a monitor of the structural perfection with regard to interface and alloy disorder. key words: resonant tunnelling diode, high-speed electronics, terahertz, photoluminescence