Undoped Channel Research Articles

A computational analysis of the impact of thin undoped channels in surface-related current collapse of AlGaN/GaN HEMTs

Abstract This study provides an insight into the impact of thin purely undoped GaN channel thickness (t ch) on surface-related trapping effects in AlGaN/GaN high electron mobility transistors. Our TCAD study suggests that in cases where parasitic gate leakage is the driving trapping mechanism that promotes the injection of electrons from the Schottky gate contact into surface states, this effect can be alleviated by reducing t ch of the undoped GaN channel. We show that by decreasing t ch from 130 to 10 nm, devices exhibit a reduction in gate-related current collapse under the specific class-B RF operating bias conditions as a consequence of a substantial decrease in the off-state gate leakage with reducing t ch. Large-signal simulations revealed an increase by 3 W mm−1 and about 12% output power and power-added efficiency due to the decrease of gate-related collapse. This work, for the first time, highlights the role of a proper purely undoped GaN t ch selection to alleviate gate-related surface trapping in the design of GaN-based microwave power amplifiers.

A High-Performance InGaAs Vertical Electron-Hole Bilayer Tunnel Field Effect Transistor with P+-Pocket and InAlAs-Block.

To give consideration to both chip density and device performance, an In0.53Ga0.47As vertical electron-hole bilayer tunnel field effect transistor (EHBTFET) with a P+-pocket and an In0.52Al0.48As-block (VPB-EHBTFET) is introduced and systematically studied by TCAD simulation. The introduction of the P+-pocket can reduce the line tunneling distance, thereby enhancing the on-state current. This can also effectively address the challenge of forming a hole inversion layer in an undoped InGaAs channel during device fabrication. Moreover, the point tunneling can be significantly suppressed by the In0.52Al0.48As-block, resulting in a substantial decrease in the off-state current. By optimizing the width and doping concentration of the P+-pocket as well as the length and width of the In0.52Al0.48As-block, VPB-EHBTFET can obtain an off-state current of 1.83 × 10-19 A/μm, on-state current of 1.04 × 10-4 A/μm, and an average subthreshold swing of 5.5 mV/dec. Compared with traditional InGaAs vertical EHBTFET, the proposed VPB-EHBTFET has a three orders of magnitude decrease in the off-state current, about six times increase in the on-state current, 81.8% reduction in the average subthreshold swing, and stronger inhibitory ability on the drain-induced barrier-lowering effect (7.5 mV/V); these benefits enhance the practical application of EHBTFETs.

Physical insight of thin AlGaN back barrier for millimeter-wave high voltage AlN/GaN on SiC HEMTs

In this work, physical mechanisms underlying carbon-doped buffer combined with an AlGaN back-barrier layer are investigated in state-of-the-art millimeter-wave AlN/GaN transistors. We have fabricated devices with and without the insertion of a thin AlGaN back-barrier layer with reduced carbon concentration to analyze the improvement resulting from this buffer architecture. More specifically, the impact of the Al mole fraction into the back-barrier, carbon doping in the buffer, and channel thickness on 100 nm gate length device performance has been studied. It appears that a 150 nm undoped GaN channel followed by a highly carbon-doped GaN buffer results in good electron confinement at the expense of a high current collapse. On the other hand, an Al mole fraction of 25% in the AlGaN back barrier layer coupled with a 150 nm undoped GaN channel provides excellent electron confinement, resulting not only in a low DIBL under high electric field but also low current collapse. Calibrated on experimental devices, TCAD simulations reveal that the electric field penetration inside the GaN buffer is prevented owing to a strong polarization from the back barrier when the Al-content is high enough. That is why, the electron confinement is superior for the 25% Al mole fraction in the back barrier along with reduced current collapse. As a result, careful engineering of the carbon concentration together with the undoped GaN channel thickness is crucial to achieve robust devices, which can, thus, deliver high device performance with superior voltage operation while using short gate lengths.

Effects of Mg Doping to a LiCoO2 Channel on the Synaptic Plasticity of Li Ion-Gated Transistors.

Artificial synapses with ideal functionalities are essential in hardware neural networks to allow for energy-efficient analog computing. However, the realization of linear and symmetric weight updates in real synaptic devices has proven challenging and ultimately limits the online training capabilities of neural network systems. Herein, we investigate the effect of Mg doping on a LiCoO2 (LCO) channel in a Li ion-gated synaptic transistor, so as to improve long-term and short-term plasticity. Two transistor structures, based on a lithium phosphorus oxynitride electrolyte, were examined by using undoped LCO and Mg-doped LCO as the channel material between the source and drain electrodes. It was found that Mg doping increased the initial channel conductance by 3 orders of magnitude, which is probably due to the substitution of Co3+ by Mg2+ and the compensation of hole creation. It was further found that the doped channel transistor showed good retention characteristics and better linearity of long-term potentiation and depression when voltage pulses were applied to the gate electrode. The improved retention and linearity are attributed to an extended range of the insulator-to-conductor transition by Mg doping and Li-ion extraction/insertion cooperated in the LCO channel. Using the obtained synaptic weight update, artificial neural network simulations demonstrated that the doped channel transistor shows an image recognition accuracy of ∼80% for handwritten digits, which is higher than ∼65% exhibited by the undoped channel transistor. Mg doping also improved short-term plasticity such as paired-pulse facilitation/depression and Hebbian spike timing-dependent plasticity. These results indicate that elemental doping to the channel of Li ion-gated synaptic transistors could be a useful procedure for realizing robust neuromorphic systems based on analog computing.

Trapping Layers Prevent Dopant Segregation and Enable Remote Doping of Templated Self-Assembled InGaAs Nanowires.

Selective area epitaxy is a promising approach to define nanowire networks for topological quantum computing. However, it is challenging to concurrently engineer nanowire morphology, for carrier confinement, and precision doping, to tune carrier density. We report a strategy to promote Si dopant incorporation and suppress dopant diffusion in remote doped InGaAs nanowires templated by GaAs nanomembrane networks. Growth of a dilute AlGaAs layer following doping of the GaAs nanomembrane induces incorporation of Si that otherwise segregates to the growth surface, enabling precise control of the spacing between the Si donors and the undoped InGaAs channel; a simple model captures the influence of Al on the Si incorporation rate. Finite element modeling confirms that a high electron density is produced in the channel.

Undoped p-type ZnTe thin film and thin film transistor channel performance

Undoped p-type ZnTe thin film and thin film transistor channel performance

Impact of the Channel Thickness on Electron Confinement in MOCVD‐Grown High Breakdown Buffer‐Free AlGaN/GaN Heterostructures

The 2D electron gas (2DEG) confinement on high electron mobility transistor (HEMT) heterostructures with a thin undoped GaN channel layer on the top of a grain‐boundary‐free AlN nucleation layer is studied. This is the first time demonstration of a buffer‐free epi‐structure grown with metal–organic chemical vapor deposition with thin GaN channel thicknesses, ranging from 250 to 150 nm, without any degradation of the structural quality and 2DEG properties. The HEMTs with a gate length of 70 nm exhibit good DC characteristics with peak transconductances of 500 mS mm−1and maximum saturated drain currents above 1 A mm−1. A thinner GaN channel layer improves 2DEG confinement because of the enhanced effectiveness of the AlN nucleation layer acting as a back‐barrier. An excellent drain‐induced barrier lowering of only 20 mV V−1at aVDSof 25 V and an outstanding critical electric field of 0.95 MV cm−1are demonstrated. Good large‐signal performance at 28 GHz with output power levels of 2.0 and 3.2 W mm−1and associated power‐added efficiencies of 56% and 40% are obtained at aVDSof 15 and 25 V, respectively. These results demonstrate the potential of sub‐100 nm gate length HEMTs on a buffer‐free GaN‐on‐SiC heterostructure.

Impact of undoped channel thickness and carbon concentration on AlN/GaN-on-SiC HEMT performances

We report on a vertically scaled AlN/GaN high electron mobility transistor technology design optimization for millimeter-wave applications. The undoped GaN channel thickness and carbon concentration into the buffer are extensively varied and systematically characterized. It is found that a thin GaN channel, typically below 150 nm improves the electron confinement, but increases the trapping effects, especially when using shorter gate lengths. Moreover, high carbon concentration into the buffer enables not only high electron confinement but also low leakage current under a high electric field at the expense of trapping effects. As a result, the optimum epi-design enabled state-of-the-art RF performances at 40 GHz.

Mathematical Modeling of Drain Current Estimation in a CSDG MOSFET, Based on La2O3 Oxide Layer with Fabrication-A Nanomaterial Approach.

In this work, three-dimensional modeling of the surface potential along the cylindrical surrounding double-gate (CSDG) MOSFET is proposed. The derived surface potential is used to predict the values of electron mobility along the length of the device, thereby deriving the drain current equation at the end of the device. The expressions are used for modeling the symmetric doped and undoped channel CSDG MOSFET device. This model uses Pao-Sah’s double integral to derive the current equation for the concentric cylindrical structure of the CSDG MOSFET. The three-dimensional surface potential estimation is performed analytically for doped and undoped device parameters. The maximum oxidant concentration of the oxide layer is observed to be 4.37 × 1016 cm−3 of the thickness of 0.82 nm for (100) and 3.90 × 1016 cm−3 of the thickness of 0.96 nm for (111) for dry oxidation, and 2.56 × 1019 cm−3 of thickness 0.33 nm for (100) and 2.11 × 1019 cm−3 of thickness 0.49 nm for (111) for wet oxidation environment conditions. Being an extensive analytical approach, the drain current serves the purpose of electron concentration explicitly inside the concentric cylindrical structures. The behavior of the device is analyzed for various threshold conditions of the gate voltage and other parameters.

Binary-Synaptic Plasticity in Ambipolar Ni-Silicide Schottky Barrier Poly-Si Thin Film Transistors Using Chitosan Electric Double Layer.

We propose an ambipolar chitosan synaptic transistor that effectively responds to binary neuroplasticity. We fabricated the synaptic transistors by applying a chitosan electric double layer (EDL) to the gate insulator of the excimer laser annealed polycrystalline silicon (poly-Si) thin-film transistor (TFT) with Ni-silicide (NiSi) Schottky-barrier source/drain (S/D) junction. The undoped poly-Si channel and the NiSi S/D contact allowed conduction by electrons and holes, resulting in artificial synaptic behavior in both p-type and n-type regions. A slow polarization reaction by the mobile ions such as anions (CH3COO− and OH−) and cations (H+) in the chitosan EDL induced hysteresis window in the transfer characteristics of the ambipolar TFTs. We demonstrated the excitatory post-synaptic current modulations and stable conductance modulation through repetitive potentiation and depression pulse. We expect the proposed ambipolar chitosan synaptic transistor that responds effectively to both positive and negative stimulation signals to provide more complex information process versatility for bio-inspired neuromorphic computing systems.

(Digital Presentation) Diffusion and Segregation in Highly Stacked Ge0.9Sn0.1/Ge:B and Ge0.95Si0.05/Ge:P Epilayers

GeSn and GeSi are promising channel materials for gate-all-around (GAA) devices to achieve the high ION thanks to the high mobility [1, 2]. The undoped channels are used to reduce the impurity scattering and to further enhance the mobility. The GAA structure with high number of stacked channels can further enhance the ION for a fixed footprint. The dopant diffusion and segregation play an important role on GAA device structure design. In this work, the dopant diffusion and segregation effects of B and P in highly stacked Ge0.9Sn0.1 and Ge0.95Si0.05 epilayers are investigated, respectively.The Ge:B/Ge0.9Sn0.1/Ge:B epilayers were grown on the Ge-buffered SOI substrate at 320°C and 100 torr by chemical vapor deposition (CVD) using SnCl4, Ge2H6, and B2H6 precursors. The 160nm undoped Ge buffer was grown with an 800℃ annealing to confine the misfit dislocations at Ge/Si interface. For the 8 stacked Ge0.9Sn0.1 epilayers, 36 nm Ge0.9Sn0.1 layers sandwiched by 24 nm Ge:B layers were grown. Transmission electron microscopy (TEM) image of Ge:B/Ge0.9Sn0.1/Ge:B epilayers is shown in Fig. 1(a). The Ge:P/Ge0.95Si0.05/Ge:P epilayers were grown on the Ge-buffered SOI substrate at 350°C and 100 torr by SiH4, GeH4, and PH3 precursors using similar Ge buffer layers. For the 8 stacked Ge0.95Si0.05 epilayers, 24 nm Ge0.95Si0.05 layers sandwiched by 25 nm Ge:P layers were grown. TEM image of Ge:P/Ge0.95Si0.05/Ge:P epilayers is shown in Fig. 1(b). Note that both Ge0.9Sn0.1 and Ge0.95Si0.05 channel layers are unintentionally doped. In the 8 stacked Ge0.9Sn0.1 epilayers, the [B] in the Ge:B layers is as high as ~2.0 ×1021 cm−3 (Fig. 2(a)). In the 8 stacked Ge0.95Si0.05 epilayers, the [P] in the Ge:P layers is as high as ~2.2 × 1020 cm−3 , and the minimum [P] in the Ge0.95Si0.05 channel layers is from ~4.2 ×1017 cm−3 to ~1.5 ×1018 cm−3 (Fig. 2(b)).The B and P diffusion phenomena in the GeSn and GeSi layers are investigated, respectively. The deep undoped GeSi layers have higher [P] due to higher thermal budget (Fig. 3). Note that the P atoms diffuse from the Ge:P layers into GeSi channels during the epitaxial growth. The similar [B] ~3x1016cm-3 in the 2nd to 8th GeSn layers is due to the B detection limit of SIMS analysis (Fig. 3). Note that the decay length (nm/decade) is defined in Fig. 4 and Fig. 5. The decay length of [B] on the top side (4.3 nm/decade) is larger than that on the bottom side (2.9 nm/decade) due to SIMS knock-on effect [3] (Fig. 4). On the other hand, the P segregation [4] increases the decay length on the bottom side of GeSi layers (Fig. 5). Both the decay length of [B] and [P] increase with the increasing depth (Fig. 6) due to the higher thermal budget of the deeper layers in the CVD chamber. In addition, the difference of [B] decay length between top and bottom sides increases with the increasing depth of epilayers (Fig. 6). For the Ge:P/GeSi/Ge:P epilayers, the difference between top and bottom [P] decay length (less than 0.9 nm/decade) is smaller than that of [B] decay length in Ge:B/GeSn/Ge:B epilayers (larger than 1.4 nm/decade) due to P segregation, and the difference decreases for deep layers.AcknowledgmentThis work is supported by the Ministry of Science and Technology, Taiwan (MOST 110-2622-8-002-014-, 110-2218-E-002-030-, and 110-2218-E-002-042-MBK) and the Ministry of Education, Taiwan (NTU-CC-110L892601). The support by Taiwan Semiconductor Research Institute (TSRI), Hsinchu, Taiwan, is also highly appreciated.

Simulation Study of Gate-Drain Leakage Current and Density of Polarization Charge at Heterojunction Interface in GaN HEMTs

In previous report, we showed that the source-drain leakage current at off state can be suppressed by thinning the undoped channel layer even if the gate length was reduced to 25 nm in device simulation of AlGaN/GaN HEMT. On the other hand, if the source-drain leakage current can be suppressed, leak current is dominated by the leakage current between the gate and drain. In this report, the source-drain leakage current and the gate-drain leakage current are calculated when drain voltage is until 50 V. When the sufficiently small access resistance is assumed, change of Al composition of barrier has almost no effect in DC characteristics, while the gate-drain leakage is suppressed when Al composition is lower due to lower polarization charge at heterojunction. To use high Schottky barrier height of the gate of AlGaN layer with high Al composition effectively, reduction of the density of polarization charge by using semi-polar-face is proposed.

Dependence of Electrical Characteristics on Epitaxial Layer Structure of AlGaN/GaN HEMTs Fabricated on Freestanding GaN Substrates

This article reports a systematic study on the effects of the epitaxial layer structure on the electrical characteristics of AlGaN/GaN high electron mobility transistors (HEMTs) fabricated on freestanding GaN substrates. First, GaN-on-GaN HEMTs were fabricated comprising channel and buffer layers unintentionally doped with Fe atoms those were diffused from the substrate. Their electrical characteristics were compared with GaN-on-SiC HEMTs. The tradeoff relation between maximum drain current and the breakdown characteristics was improved in GaN-on-GaN devices than in GaN-on-SiC devices. A small current collapse was observed in GaN-on-GaN devices despite a high Fe density in the channel. This suggested an influence of Fe diffusion on the frequency dispersion to be comparatively limited. Second, GaN-on-GaN HEMTs were fabricated using a thin undoped channel layer grown on Fe-doped GaN substrate directly or through an Fe diffusion stopper layer. Without the stopper layer, the buffer leakage was significantly increased by reducing the channel thickness, and a 100-nm-thick channel device showed nonpinch-off characteristics. On the other hand, samples with the stopper layer exhibited no buffer leakage and a complete pinchoff up to 200 V. In addition, a sample with an intentional C doping to the buffer layer showed a relatively large current collapse, suggesting a major contribution of C-doping to the frequency dispersion of GaN-on-GaN HEMTs.

A dual gate material tunnel field effect transistor model incorporating two‐dimensional Poisson and Schrodinger wave equations

AbstractThis paper presents an accurate analytical model of surface potential and drain current for a long channel dual material gate (DMG) tunneling field‐effect transistor (TFET) with the addition of nonlinear inversion charge developed at the channel/drain interface region, ambipolar characteristic, and quantum confinement. The model includes the effect of dual metal gate work function as it controls the threshold voltage without considering a fully depleted undoped channel region. The current model includes the effect of charge accumulation at the interface of two gates and an appropriate mathematical expression of nonlinear inversion charge developed at the interface of two gates has been derived from the two‐dimensional (2D) Schrodinger wave equation incorporating quantum confinement. The model is effective to capture transfer characteristics at Sub 10 nm body thickness. A high ION/IOFF ratio and less than 27 mV/decade subthreshold swing are achieved at 2 nm body thickness which is desirable for low power VLSI application. The proposed model has been compared and calculated by Sentaurus TCAD with fair accuracy and a good resemblance, including ambipolar characteristics at sub 10 nm body thickness has been achieved.

Vertically Stacked High Mobility GeSi nGAAFETs

Si FinFET architecture has been used in mass production in the industry for advanced technology nodes. Thin and tall fin for high drive current is needed for further scaling by FinFETs. However, fin aspect ratio and lithography limitation may be problematic issues. Recently, vertically stacked channel GAAFETs become good candidates to achieve better power-performance properties than FinFETs for the given footprint. The evolution to the stacked GAAFETs mitigates the patterning challenges by well-controlled epitaxy and high etching selectivity to achieve high performance and good electrostatics. The state-of-the-art stacked Si channel n/pGAAFETs and stacked Ge channel pGAAFETs have been reported. In this study, we demonstrate vertically stacked tensily strained GeSi nGAAFETs. The stacked GeSi nGAAFETs provide a possible solution to achieve high performance and to improve the electrostatics for Ge-based channel GAAFETs.The Ge/Ge0.85Si0.15 and Ge/Ge0.98Si0.02 multilayers are epitaxially grown on SOI substrates by CVD epitaxy. Ge buffer layers and sacrificial layers are not only used to achieve etching selectivity over GeSi layers to form the vertically stacked GeSi channels, but also used to provide tensile strain for GeSi n channels. Undoped channels and heavily doped sacrificial layers are used to reduce the impurity scattering and S/D resistance, respectively. The following PMA, laser annealing, and NiGe contacts formation for nFETs can further reduce the parasitic resistance to reveal the intrinsic merit of the high mobility GeSi channels.For GeSi nFETs, [Ge] larger than 85% in GeSi can ensure L valley conduction for small conductive effective mass to achieve high mobility. The △Ec between GeSi and Si is nearly zero and can be negligible. As a result, electron can flow through stacked GeSi channels and Si channel underneath for the nFETs. An engineering solution is provided to improve the electrostatic behaviors of Ge-based channels GAAFETs. We demonstrate the vertically stacked Ge0.85Si0.15 channels above a Si channel, which has good subthreshold behaviors. The VT difference between Ge0.85Si0.15 and Si can be tuned by the channel size optimizing. By narrowing the Ge0.85Si0.15 channel size to 5nm, the bandgap can be increased by quantum confinement and the short channel effect can be suppressed. As a result, more positive VT for Ge0.85Si0.15 than Si is observed. Therefore, the underneath Si channel with good electrostatic turn on first and dominate the subthreshold region. Good SS=76mV/dec and low DIBL=36mV/V are obtained due to low Dit and good short channel control. IOFF is also dramatically reduced and the ION/IOFF is improved to be 1.2E7 thanks to the increase of the bandgap and the improved short channel control for the narrow Ge0.85Si0.15 channels. The improved flicker noise of optimized channel size also indicates the enhanced reliability.To increase [Ge] in channel layers for mobility enhancement, Si incorporation as small as 2% into Ge can achieve sufficient etching selectivity of heavily phosphorus-doped Ge sacrificial layers over undoped Ge0.98Si0.02 to form two stacked Ge0.98Si0.02 nanowire channels, and introduce 0.27% uniaxial tensile strain for the electron mobility enhancement. The alloy scattering is still minimal for 2% Si. An additional 800oC anneal after the Ge buffer growth further improves the epi quality by confining misfit dislocations near the Ge buffer/Si interface. However, the Dit at Si underneath channel/dielectrics interface may be poor due to misfit dislocations confinement. As a result, the parasitic Ge/Si channel underneath the Ge0.98Si0.02 channels is completely removed by optimized etching. The distinct photoresponse of the floating channels and the parasitic channels can be a signature and provide a non-destructive method to check the existence of the parasitic channels. The photoresponse of the sole parasitic channel mainly shows the photocurrent (Iph), while the photoresponse of the sole floating channels without parasitic channel yields the negative threshold voltage shift (ΔVT) for nFETs. The device with both floating channels and the parasitic channel shows both photocurrent and negative threshold voltage shift under exposure. ION can be enhanced by scaled LG and large channel cross section. Record ION of 48μA per stack at VOV=VDS=0.5V and record Q (Gm,max/SSSAT) of 8.3 at VDS=0.5V with LG=40 nm are achieved among Ge nFETs.CVD grown Ge nGAAFET is compatible with Si technology. Excellent electrical characteristics are achieved and the results are comparable to mature Si nFETs. Indicating vertically stacked high mobility channel is promising candidate for CMOS applications in the future technology nodes to further extend the Moore’s law.Acknowledgements: This work is supported by MOST (MOST 109-2218-E-002-031- and 108-2622-8-002-016-) and MOE (NTU-CC-109L891601), Taiwan. The support from Taiwan Semiconductor Research Institute is also highly appreciated.

Thickness Trends of Electron and Hole Conduction and Contact Carrier Injection in Surface Charge Transfer Doped 2D Field Effect Transistors.

One of the main limiting factors in the performance of devices based on two-dimensional (2D) materials is Fermi level pinning at the contacts, which creates Schottky barriers (SBs) that increase contact resistance and, for most transition metal dichalcogenides (TMDs), limit hole conduction. A promising method to mitigate these problems is surface charge transfer doping (SCTD), which places fixed charge at the surface of the material and thins the SBs by locally shifting the energy bands. We use a mild O2 plasma to convert the top few layers of a given TMD into a substoichiometric oxide that serves as a p-type SCTD layer. A comprehensive experimental study, backed by TCAD simulations, involving MoS2, MoSe2, MoTe2, WS2, and WSe2 flakes of various thicknesses exposed to different plasma times is used to investigate the underlying mechanisms responsible for SCTD. The surface charge at the top of the channel and the gate-modulated surface potential at the bottom are found to have competing effects on the channel potential, which results in a decrease in the doping-induced threshold shift and an increase in minimum OFF state current with increasing thickness. Additionally, an undoped channel region is shown to mitigate carrier injection issues in sufficiently thin flakes. Notably, the band movements underlying the SCTD effects are independent of the particular semiconductor material, SCTD strategy, and doping polarity. Consequently, our findings provide critical insights for the design of high-performance transistors for a wide range of materials and SCTD mechanisms including TMD devices with strong hole conduction.

Ultrafast Photocurrent Response and High Detectivity in Two-Dimensional MoSe2-based Heterojunctions.

Two-dimensional (2D) transition metal dichalcogenide (TMDC) materials have garnered great attention on account of their novel properties and potential to advance modern technology. Recent studies have demonstrated that TMDCs can be utilized to create high-performing heterostructures with combined functionality of the individual layers and new phenomena at these interfaces. Here, we report an ultrafast photoresponse within MoSe2-based heterostructures in which heavily p-doped WSe2 and MoS2 flakes share an undoped MoSe2 channel, allowing us to directly compare the optoelectronic properties of MoSe2-based heterojunctions with different 2D materials. Strong photocurrent signals have been observed in both MoSe2-WSe2 and MoSe2-MoS2 heterojunctions with a photoresponse time constant of ∼16 μs, surmounting previous MoSe2-based devices by three orders of magnitude. Further studies have shown that the fast response is independent of the integrated 2D materials (WSe2 or MoS2) but is likely attributed to the high carrier mobility of 260 cm2 V-1 s-1 in the undoped MoSe2 channel as well as the greatly reduced Schottky barriers and near absence of interface states at MoSe2-WSe2/MoS2 heterojunctions, which lead to reduced carrier transit time and thus short photocurrent response time. Lastly, a high detectivity on the order of ∼1014 Jones has been achieved in MoSe2-based heterojunctions, which supersedes current industry standards. These fundamental studies not only shed light on photocurrent generation mechanisms in MoSe2-based heterojunctions but also open up new avenues for engineering future high-performance 2D optoelectronic devices.

Simulation of the Short Channel Effect in GaN HEMT with a Combined Thin Undoped Channel and Semi-Insulating Layer

Simulation of the Short Channel Effect in GaN HEMT with a Combined Thin Undoped Channel and Semi-Insulating Layer

Total Ionizing Dose Responses of Forward Body Bias Ultra-Thin Body and Buried Oxide FD-SOI Transistors

This paper investigates the total ionizing dose (TID) responses of forward body bias (FBB) ultrathin body and buried oxide fully depleted silicon-on-insulator (UTBB FD-SOI) transistors, which are commonly used in commercial foundries. The experimental results demonstrate that TID-induced threshold voltage shift in FBB nMOSFET cannot be mitigated by applying biasing to back-gate (back-gate biasing). Bias condition dependence has also been explored, revealing that building up of the oxide-trapped charge (Not) in the buried oxide is affected by the electric field induced by the space charge. Moreover, the effect of threshold voltage option on TID responses of UTBB FD-SOI transistors with the undoped channel was first explored. Finally, the TID-enhanced back-gate biasing controlling of the threshold voltage was observed, which is a new phenomenon for the TID responses of UTBB FD-SOI transistors.

Compact modeling of strained GAA SiNW

<span>Strain-based on advanced MOSFET is a promising candidate for the future of CMOS technology. A numerical model is not favorable compared to a compact model because it cannot be integrated into most simulator software. Thus, a compact model is proposed to overcome the shortcomings in the analytical model. In this paper, a charge-based compact model is presented for long-channel strained Gate-All-Around Silicon Nanowire (GAA SiNW) from an undoped channel to a doped body. The model derivation is based on an inversion charge which has been solved explicitly using the smoothing function. The drain current model is formulated from Pao Sah’s dual integral which is formed in terms of inversion charge at the drain and source terminals. The proposed model has been extensively verified with the numerical simulator data. The strained effect on the electrical parameters are studied based on inversion charge, threshold voltage and current-voltage (I-V) characteristics. Results show that the current, the inversion charge and the threshold voltage can be greatly improved by the strain. The threshold voltage was reduced approximately 40% from the conventional GAA SiNW. Moreover, the inversion charge was improved by 30 % and the on-state current has doubled compared to unstrained device.</span>