Underlap FinFET Research Articles

Design Considerations into Circuit Applications for Structurally Optimised FinFET

FinFETs have gained a lot of demand in the family of multigate FET devices in the recent years. In this view, this manuscript aims to design different FinFET architectures to observe the analog and circuit performance. A total of five structures namely Conventional FinFET, Lightly doped S/D, Underlap FinFET, Single-k spacer, and Dual-k spacer FinFET has been designed and performance has been analysed. The best performance is obtained for dual-k spacer FinFET. Moreover, the dimensional variations such as gate length (Lg), fin width (Wfin) and fin height (Hfin) for the duak-k spacer FinFET is performed and it is found that lowering the Lg and Wfin, and increasing the Hfin would be a better option in order to enhance the device performance. Furthermore, at the optimized device dimensions the circuit analysis for inverter and single stage common source amplifier is performed. The gain for the designed single stage common stage amplifier is noticed to be 1.8155.

Analysis of Underlap Tri-Gate FinFET and Its Capacitance Effects for Analog/Radio Frequency Applications

Manufacturing ultra-scaled FinFET devices has become a massive obstacle for device engineers. The critical challenge experienced Multi-Gate FETs is process variation; Consequently, devices’ performances are impacted and analyzed for device performance losses due to misalignments of gate locations close to sources and drain edgess (lower regions). FinFET is examined using a 3D mathematical model, the impact of base gate areas on variables such as electric fields, surface channel potentials, subthreshold oscillations, threshold voltages, and drainage-induced barrier reductions and effects beneath coating. 3D simulators validate the outcomes yielded by the model. The advantage of underlap FinFET of streamlining investigates the spacer dielectric material (low k and high k) and its underlapped Gate length using the TCAD simulator.

The Impact of Spacer Oxide Material on the Underlapped SOI-nFinFET Working as Charged Based Radiation Sensor

In this work, the influence of the underlap region on the electrical behavior of a SOI-nFinFET transistor has been studied with the purpose of radiation sensing. The analysis was performed by evaluating the impact of variations in the underlap region on the on-state current and by studying its sensitivity. The impact of the underlap region on the drain current and, consequently, on the devices’ sensitivity was explained by the analysis of series resistance, the fringing field and electron density. Considering the main impact of radiation in these devices, the study of sensitivity was also performed taking into consideration the variation of oxide trapped charges density. When applying the transistor to a harsh environment, the Underlapped FinFET showed to be a quite respectable radiation sensor, since the results performed with very good sensitivities when using long and narrow spacer oxide with low permittivity oxide. With thicker spacer oxide in the underlap region, the charge concentration makes the spreading field high enough to overcome the series resistance effect, which results in a less sensible device. Once presented the on-state current variation of the Underlapped FinFET, the study turns radiation-sensing purpose applicable using the excellent characteristics of this device, which is shown in detail throughout this work.

FinFET based SRAMs in Sub-10nm domain

An exponential rise in transistor count, have increased the power consumption of the modern digital system. Moreover, at lower technology node, the performance of conventional CMOS designs degrades because of the short channel effects (SCEs). In sub-10 ​nm technologies, FinFET devices have good gate control and achieve superior performance than CMOS designs. FinFET devices possess high ION current and improved scalability compared to conventional CMOS. Among numerous double gate (DG) devices, the quasiplanar FinFET structure gained huge attention because of the simple fabrication process [4]. However, FinFET based designs have a major width quantization issue. The width of FinFET device varies only in quanta of silicon fin height (HFIN) [4]. This is a critical issue for ratioed designs like Static Random-Access Memory (SRAMs), where proper sizing of transistors is essential for correct functionality. With process variations, this issue becomes even worse and affect the performance of SRAM cell. The SRAM has a significant performance impact on current nanoelectronics systems. Next-generation devices overcome the short-channel effects (SCE) of CMOS technology and can be used to improve the efficiency of SRAM designs. FinFETs are promising emerging devices, which can improve the performance of SRAM designs at lower technology nodes. This review paper presents different types of SRAM bitcells and memory system architectures. It also discusses the detailed analysis of SRAM bitcells based on various highly explored FinFET devices in sub-10nm domain. The read stability and write ability of SRAM cells are determined using Static Noise Margin (butterfly) and N-curve methods. Moreover, this manuscript presents a benchmarking between the Underlapped FinFET based SRAM and Design Technology Optimized FinFET Based SRAM. In addition to this, Monte Carlo simulations are performed on the SRAM cells to evaluate process variations to determine the robustness of SRAM designs. Simulations were done in HSPICE using 7 ​nm technology.

Subthreshold Performance Improvement of Underlapped FinFET Using Workfunction Modulated Dual-metal Gate Technique

Workfunction modulated dual material gate FinFET (WMDMG-FinFET) is proposed to improve the DC performance of the device. A dual metal gate FinFET with linear modulation in workfunction along the source side of gate electrode keeping drain side gate electrode workfunction to be constant is introduced. Its subthreshold performance (i.e., switching ratio and subthreshold swing) is enhanced by introducing spacers in the side-walls of gate, with underlap concept. SILVACO TCAD tool is used to carry out the simulation work. The simulation results are compared for different spacers and it is observed that TiO2 spacer with high-k dielectric gives the best switching ratio and lowest subthreshold swing. The WMDMG-FinFET with spacers in the underlapped region shows better subthreshold characteristics as compared to conventional DMG-FinFET.

Study of Underlapped Finfets Behavior for a Radiation Sensing Purpose

The use of MOSFET transistors as radiation sensors has been intensively studied in recent years. Since the main effects caused by the total ionization dose (TID) are well known, the application of this technology as a dosimeter for many applications has greatly increased. One example is the application of MOSFETs as dosimeter of Radiotherapy (1). Knowing that SOI FinFETs have high immunity to soft errors and thin FinFET devices also presents a good radiation hardness for TID effects, the Underlapped FinFET structure can be applied as an accurate radiation sensor since only the oxide in the underlap region will be responsible for the drain current (ID) variation.The experimental behavior of self-aligned FinFET transistor with fin width (WFIN) of 20nm before and after proton irradiation are presented in figure 1. As already reported in (2, 3), the FinFET with WFIN=20 nm shows a high immunity to TID effects of proton radiation even considering the accumulated charges in the front and buried oxides due to the high coupling between gates.From now on, it was considered the underlap regions for both source and drain (S/D) sides. The simulation was calibrated with experimental FinFET behavior for self-aligned structure and it was extrapolated for other underlapped structures varying the underlap lengths (LSP). The underlap region was varied from 0nm (self-aligned structure) to 50nm and the permittivity (k) of the oxide in the underlap region was varied from 1 (no oxide in the underlap region) to 25 (hafnium oxide – HfO2). Figure 2 presents the drain current as a function of gate voltage (VG) for underlapped FinFETs, varying the underlap length and the permittivity of the oxide in the underlap region. The increase of the LSP results in a strong degradation of ID due to the loss charge control over the underlap, caused by lower electric field effect (fringing field), which increases the series resistance and the current spreading in the spacer.Besides the underlap length, the impact of permittivity on the on-state current level (ION) can also be observed in figure 2. The permittivity increase results in a higher fringing fields from the gate to the source/drain regions and consequently a higher current density, that in turns, causes the improvement on ION. The electric field and the electron density were extracted from numerical simulations for devices with k=1 and k=25 and a higher fringing field and consequently the higher electron density over the underlap region, for devices with k=25, can be observed in figure 3.The sensitivity (S), that was calculated by ID (k=X)/ID (k=1), was evaluated in order to select the better oxide and length to the underlap region. From figure 4, it is possible to observe that the greater the LSP and permittivity, the better is the sensitivity of the device. Although devices with longer underlap present a high series resistance and consequently a smaller drain current level, the ION enhancement caused by the higher influence of fringing field becomes more pronounced when using the higher permittivity, resulting in a more sensitive device. However, for high drain bias (VDS=1V) the underlap length plays a hole until LSP=30 nm, for longer underlap no significant sensitivity variation was obtained.Considering that the device with longer underlap region (LSP=50nm) and higher k (HfO2 – k=25) presents a better sensitivity, it was considered to evaluate its charges sensing ability.Aiming to analyze the underlapped FinFET as a radiation sensor (TID), fixed charges density (Qox) with carrier concentration of 0, 1011, 5x1011 and 1012 cm-2 were considered in the underlap region, where Qox=0 cm-2 characterizes the pre-radiated transistor. Figure 5 shows that despite the low on-state current caused by the high series resistance, when the oxide charges are considered, there is an increase of the potential in the underlap region causing an enhancement of ION. The radiation sensitivity was calculated by post-radiated ION over pre-radiated ION ratio.Although narrow FinFETs are well known as a radiation hardness transistor, from figure 6 it is possible to notice that a long underlap region with a high k dielectric allows this device to have a good sensing behavior. When considering a relatively low trapped charge density (Qox= 5x1011cm-2), the drain current increases about 60%, i.e., sensitivity equal 1.6. Increasing the trapped charge density to Qox=1x1012 cm-2, the obtained sensitivity values are still higher, reaching an increment of 140% on the ION current level (S=2.4), confirming the excellent characteristic of the device working as a radiation sensor. Figure 1

Study of Underlapped Finfets Behavior for a Radiation Sensing Purpose

In this paper the electrical characteristics of the Underlapped FinFET transistor is studied for different underlap lengths and underlap oxide material. Disturbs caused by underlap region, such as series resistance effect and the spreading electric field have been evaluated. Besides the underlap length, the impact of oxide permittivity on the on-state current level, fringing fields increasing and on current density was also evaluated. When analyzing the Underlapped FinFET as a radiation sensor, the better sensitivity was obtained for long underlap regions and for transistor biased with high drain voltage. The potential increasing in the underlap region results in on-state current enhancement, which characteristic allows this device present good response for sensing purposes.

10 nm TriGate High k Underlap FinFETs: Scaling Effects and Analog Performance

Nano scale devices with improved performance than the conventional CMOS devices is of great need in recent days. The paper investigates the performance of 10 nm Trigate FinFET structure with high k dielectric spacer on either side of the channel in the underlap region. The proposed structure increases the On-Off ratio (ION/ IOFF) of drain current by order of 106 and also improves the subthreshold swing (SS). Further, it enhances the transconductance (gm) at the low gate voltage, raises the output conductance (gd) and intrinsic gain (gm/gd) proving that the device provides efficient analog performance suitable for RF applications.

Low Leakage Current Symmetrical Dual-k 7 nm Trigate Bulk Underlap FinFET for Ultra Low Power Applications

The main purpose of this paper is to achieve as low as possible leakage current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> ) to meet the requirements for ultra-low power (ULP) applications. The proposed methodology is based on studying the effect of the most effective FinFET design parameters that directly impact its leakage current. The parameters explored in this paper are the effective channel lengths L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> , gate stacks, gate contact materials, and gate-sidewall spacers (L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sp</sub> ). The results show that utilizing a symmetrical dual-k material for 7-nm underlap tri-gate FinFETs appreciably allows a sufficient ON current and low leakage current and hence low stand by power consumption. Specifically, the effect of spacer length L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sp</sub> and LHK is investigated to get low leakage current keeping I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> as high as possible. Moreover, the effective channel length in subthreshold conduction (L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> ) is maintained greater than the gate length (L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> ) and the threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ) is adjusted by the proper metal gate work function. The performance of the proposed nand p-FinFET devices is verified using Sentaurus TCAD simulator from Synopsys. The resulted I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> is 17 pA/μ m for n-FinFET and 14.7 pA/μm for p-FinFET which are the lowest leakage currents found in recent publications. The achieved I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> ratio for both proposed devices is found to be 12.3 x 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sup> and 11 x 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sup> , respectively, which are comparable to the published data. These parameters are obtained for an appropriate choice of L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sp</sub> = 10 nm and L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">HK</sub> = 5 nm. In addition, the short channel effects variations with LHK have been investigated.

A Hybridized Fuzzy-Neural Predictive Intelligent (HFNPI) Modelling Approach-based Underlap FinFET Model

ABSTRACTThis paper presents the hybridized fuzzy-neural predictive intelligent (HFNPI) based approach for predicting FinFET model. The proposed model is an improved approach over artificial neural network (ANN) model and adaptive neuro fuzzy inference system (ANFIS) model that provides optimum model parameters. In this paper, the challenge of optimization of large number of parameters is reduced. It assesses the performance of resultant structure on the basis of selected RF figure-of-merit. Based on the application requirements, RF figure-of-merit such as fT and fmax are used as appropriate performance parameters to analyse the device performance. The framework for the HFNPI model is underlapped FinFET structural/process parameters. The mean prediction error was found 2.8 × 10−4 GHz. The comparative analysis of HFNPI with ANN and ANFIS model is done. It is found that combination of fuzzy and neural logic shows better result rather than individual ANFIS and ANN model to redevelop the model and increase the number of inputs.

Asymmetric Drain Extension Dual-kk Trigate Underlap FinFET Based on RF/Analog Circuit.

Among multi-gate field effect transistor (FET) structures, FinFET has better short channel control and ease of manufacturability when compared to other conventional bulk devices. The radio frequency (RF) performance of FinFET is affected by gate-controlled parameters such as transconductance, output conductance, and total gate capacitance. In recent years, high-k spacer dielectric materials for manufacturing nanoscale devices are being widely explored because of their better electrostatic control and being less affected by short channel effects (SCEs). In this paper, we aim to explore the potential benefits of using different Dual-k spacers on source and drain, respectively: (AsymD-kk) trigate FinFET structure to improve the analog/RF figure of merit (FOM) for low-power operation at 14 nm gate length. It has been observed from the results that the AsymD-kk FinFET structure improves the coupling of the gate fringe field to the underlap region towards the source and drain side, improving the transconductance (gm) and output conductance (gds) at the cost of an increase in Miller capacitance. Furthermore, to reduce the drain field influence on the channel region, we also studied the effect of asymmetric drain extension length on a Dual-kk FinFET structure. It can be observed that the new asymmetric drain extension structures significantly improve the cutoff frequency (fT) and maximum oscillation frequency (fmax) given the significant reduction of inner fringe capacitance towards drain side due to the shifting of the drain extension’s doping concentration away from the gate edge. Therefore, the asymmetric drain extension Dual-kk trigate FinFET (AsymD-kkDE) is a new structure that combines different Dual-k spacers on the source and drain and asymmetric drain extension on a single silicon on insulator (SOI) platform to enhance the almost all analog/RF FOM. The proposed structure is verified by technology computer-aided design (TCAD) simulations with varying device physical parameters such as fin height, fin width, aspect ratio, spacer width, spacer material, etc. From comprehensive 3D device simulation, we have demonstrated that the proposed device is superior in performance to a conventional trigate FinFET and can be used to design low-power digital circuits.

Threshold voltage variability induced by spacer- and resist-defined patterning techniques in nanoscale FinFETs

In aggressively scaled devices, FinFET technology has become more prone to line-edge roughness (LER) induced threshold voltage variability. To explain this challenge, all possible LER-induced fin shape variabilities in spacer-defined patterning (i.e., correlated LER) and resist-defined patterning (i.e., uncorrelated LER) technology have been investigated for 14-nm underlap FinFET using 3-D numerical simulations. All LER-induced VTH variabilities are analyzed in the presence of other intrinsic variability sources, such as random dopant fluctuation (RDF), work function variation (WFV), and oxide thickness variation (OTV). This study reveals that the percentage threshold voltage (VTH) fluctuations of combined effects (RDF, WFV, and OTV) in spacer-defined and resist-defined FinFETs with respect to rectangular FinFET are 2.88% and 8.76%, respectively.

Line edge roughness induced threshold voltage variability in nano-scale FinFETs

In aggressively scaled devices, the FinFET technology has become more prone to line edge roughness (LER) induced threshold voltage variability. As a result, nano scale FinFET structures face the problem of intrinsic statistical fluctuations in the threshold voltage. This paper describes the all LER induced variability of threshold voltage for 14 nm underlap FinFET using 3-D numerical simulations. It is concluded that percentage threshold voltage (VTH) fluctuations referenced with respect to rectangular FinFET can go up to 8.76%. This work has also investigated the impact of other sources of variability such as random dopant fluctuation, work function variation and oxide thickness variation on threshold voltage.

Underlapped FinFET on insulator: Quasi3D analytical model

The work presented in this paper analyse the influence of gate underlap region (present either near the source end or near the drain end) on the performance of FinFET using an efficient quasi 3D analytical model carried out by using separation of variable technique. Various parameters analysed in this work are: surface potential, electric field, threshold voltage (Vth), Subthreshold slope (SS), Drain Induced Barrier Lowering (DIBL) and sub-threshold drain current for different channel and underlap length. Analytical results obtained from the developed model are validated by 3-D ATLAS device simulation software results. Analog and RF performance metrics are also extracted for different lengths of underlap region and compared with the conventional FinFET through extensive device simulation. The influence of the back gate voltage on the electrostatics of the underlap FinFET is also investigated. The single stage common source amplifier using conventional and underlap FinFET has also been analysed. Apart from this, switching speed of the device is also investigated by comparing Ion/Ioff ratio and delay for different underlap and channel length.

Asymmetric Underlapped FinFETs for Near- and Super-Threshold Logic at Sub-10nm Technology Nodes

Extending double-gate FinFET scaling to sub-10nm technology regime requires device-engineering techniques for countering the rise of direct source to drain tunneling (DSDT), edge direct tunneling (EDT) and short channel effects (SCE) that degrade FinFET I-V characteristics. Symmetric underlap is effective for eliminating EDT, diminishing DSDT, and lowering the fringe component of gate capacitance. However, excessive symmetric underlap also lowers the on-current, which is mainly due to thermionic emission. In this work, it is demonstrated that at sub-10nm node, asymmetric underlapped FinFETs with slightly longer underlap toward drain side than source side are superior to symmetric underlapped FinFETs due to further improvement in I on /I off and reduction in gate-to-drain capacitance. Using quantum mechanical device simulations, FinFETs with various degrees of underlap have been analyzed for improvement in I-V characteristics. A FinFET model for circuit simulations has been constructed that captures the major sub-10nm leakage components, namely, thermionic emission, DSDT, EDT, direct gate oxide tunneling and its associated components. By simulating a 10-stage NAND circuit and a LEON3 processor with interconnect parasitics using these devices, it is shown that asymmetric underlap instead of symmetric underlap in sub-10nm FinFETs can offer lower energy consumption with improved performance for near-threshold logic and higher energy-efficiency for super-threshold logic operation.

Physical Insights Into Electric Field Modulation in Dual-&lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$k$ &lt;/tex-math&gt; &lt;/inline-formula&gt; Spacer Asymmetric Underlap FinFET

In this paper, the performance of dual-k spacer asymmetric underlap FinFET (DKAU-FinFET) is analyzed. The significance of using dual-k spacers is illustrated considering the parasitic outer fringing capacitance. The study also presents physical insights into inversion charge modulation by dual-k spacers in DKAU-FinFETs. In addition, the proposed device structure is analyzed for analog, RF, and digital circuit performances. Based on the performance analysis, the use of optimum inner high-k spacer thickness is proposed for reliable device performance.

Oxide thickness and S/D junction depth based variation aware OTA design using underlap FinFET

As the gate lengths of FinFETs are scaled into nano meter regime, spatial variations in oxide thickness (Tox) and junction depth (Xj) of source/drain (S/D) doping profile will largely decide the performance of digital and analog circuits that can fall below or above the desired value. Of particular importance is operational transconductance amplifier (OTA), where the crucial analog figures of merit (FOM) such as differential mode gain (ADM), common mode gain (ACM) and common mode rejection ratio (CMRR) decide the suitability of its use at nanometer regime. In the present work, we have studied the analog performance variation of low-k (dual-k) underlap FinFET based single stage OTA with spatial variation in Tox and Xj of S/D profile. Enhanced and variation less threshold voltage and mobility of dual-k underlap FinFET due to of better screening of longitudinal field and pronounced volume inversion effect, are studied in detail. It is observed that at 16nm gate length the best case ADM, ACM and CMRR of low-k (dual-k) FinFET based OTA are 34.2dB (42.3dB), 26dBm (18dBm), 68.2dB (84.2dB) respectively. Subsequently, the spatial variation of Tox and Xj leads to worst case change in ADM and ACM of low-k (dual-k) FinFET based OTA by −6.8dB (−2.2dB) and +28.2dBm (+31.3dBm) respectively. The negligible deterioration in ACM of dual-k FinFET OTA transforms into CMRR improvements of 37% at this worst case condition as compared to CMRR of low-k FinFET OTA. Furthermore, with gate length scaling, the FOM and their percentage change with Tox and Xj of dual-k FinFET OTA are much better than that of low-k FinFET OTA.

FinFET With High-&lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$\kappa $ &lt;/tex-math&gt; &lt;/inline-formula&gt; Spacers for Improved Drive Current

We demonstrate p-channel gate-source/drain underlapped silicon FinFET with HfO2 high- $\kappa $ spacer and compare it with its counterpart having SiO2 low- $\kappa $ spacer. The HfO2 spacer structure reduces series resistance in the underlap regions due to the large capacitive coupling between the gate and the underlap regions. Both drain current and transconductance of p-channel FinFET are higher than those of the SiO2 spacer device by about $3\times $ when biased in the saturation region, and about $1.6\times $ and $2\times $ , respectively, when biased in the linear region. Subthreshold swing and drain-induced barrier lowering are also improved by incorporating the HfO2 spacer.

Impact of temperature on linearity and harmonic distortion characteristics of underlapped FinFET

In this paper, the performance of asymmetric underlapped FinFETs (U-FinFETs) is analyzed for linearity and harmonic distortion at high temperatures. The harmonic distortion that arises as a result of non-linear device characteristics requires a detailed analysis for better RF reliability performance. The variations in linearity and distortion characteristics with temperature are analyzed with regards to the primary components of harmonic distortion, second order distortion (HD2), third order distortion (HD3), and the total harmonic distortion (THD). For detailed understanding of the distortion characteristics of U-FinFETs, different device parameters such as the drain current (Ids) and transconductance (gm) are also analyzed. The results of the analysis suggest that the U-FinFETs present a significant reduction in harmonic distortion at elevated temperatures under subthreshold regime and restrict the degradation in harmonic distortion in the superthreshold regime resulting in better reliability for RF applications.

Write Assist SRAM Cell with Asymmetrical Bitline Access Transistors for Enhanced Data Stability and Write Ability

A novel six-transistor static random-access memory (6T SRAM) cell is proposed in this paper for enhancing the data stability and write ability as compared to the conventional memory circuits. Asymmetrically gate overlapped / underlapped FinFETs are employed as bitline access transistors in the proposed SRAM cell. The strength of the asymmetrical bitline access transistors are weakened during read operations. Furthermore, voltage transfer characteristics (VTCs) of cross-coupled inverters have narrower transition regions in the new SRAM cell as compared to the conventional SRAM cells. The proposed SRAM cell thereby provides stronger read data stability as compared to the conventional symmetrical SRAM cells. The strength of bitline access transistors are enhanced during write operations as the direction of current flow is reversed in the new asymmetrical SRAM cell. The power supply voltage of a selected word floats during write operations. The write voltage margin is thereby significantly increased with the proposed SRAM cell as compared to the conventional SRAM cells. The read data stability and write ability are both enhanced by up to 51.7% and 65.5%, respectively, with the proposed SRAM cell as compared to the conventional symmetrical six-FinFET SRAM cells in a 15[Formula: see text]nm FinFET technology.