Underlap Double Gate Research Articles

Study of body and oxide thickness variation on analog and RF performance of underlap DG-MOSFETs

The underlap double gate MOSFET (UDG-MOSFET) has been well established as a potential candidate for the RF applications. However, before implementation the various process related variations are required to be addressed for the better dependability. In this paper, the effect of process dependent parameter variations on the RF performance of the UDG-MOSFET is analyzed. The process dependent parameters considered are the oxide and the body thicknesses. The RF performance of UDG-MOSFET is analyzed as a function of RF figure of merits (FOMs), intrinsic capacitance (Cgs, Cgd), intrinsic resistance (Rgs, Rgd), transport delay (τm), inductance (Lsd) and analog FOMs transconductance (gm), transconductance generation factor (gm/Id), output resistance (Ro) and intrinsic gain (gmRo). The analysis is performed using the non-quasi static (NQS) small signal model of the UDG-MOSFET.

Analysis of Harmonic distortion in asymmetric underlap DG-MOSFET with high-k spacer

In analog and RF circuit applications Harmonic distortion (HD) is an important reliability issue that arises due to non-linear performance of devices. In this paper, the asymmetric underlap double gate MOSFET (AUDG-MOSFET) is analyzed for the HD with high-k spacers. In this analysis the devices are compared for their primary distortion components designated by the second order distortion (HD2), the third order distortion (HD3) and the total harmonic distortion (THD). The distortion characteristics of the device are studied as a function of the gate voltage (Vgs) and the transconductance generation factor (gm/Id) considering the influence of drain current (Id) and the transconductance (gm). A significant improvement on the HD of the device by using high-k spacers is inferred, thereby ascertaining better reliability for RF applications. In addition to this, the distortion in the output characteristics of Cascode and differential amplifier circuits designed with AUDG-MOSFET device is also analyzed in detail.

Ultra Low Power Junctionless MOSFETs for Subthreshold Logic Applications

In this paper, we report the potential of junctionless (JL) MOS transistors for ultra low power (ULP) subthreshold logic applications. It is demonstrated that double gate (DG) JL devices, which do not require source or drain extension region engineering, can perform significantly better than conventional inversion mode devices, and comparable with underlap DG MOSFETs for ULP applications. Sensitivity analysis shows that among all device parameters, JL devices exhibit least sensitivity to gate length in comparison with inversion mode and underlap MOSFETs. Results highlight the advantages and challenges of JL transistors for next-generation ULP CMOS logic devices.

Subthreshold Analog/RF Performance Enhancement of Underlap DG FETs With High- $k$ Spacer for Low Power Applications

This paper presents a systematic study of the subthreshold analog/RF performance for underlap double gate (UDG) NMOSFETs using high dielectric constant ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> ) spacers. The conventional UDG-NMOSFETs offer reduced short-channel effects along with improved subthreshold analog/RF performance at a cost of higher distributed channel resistance and low on current. In this paper, we show that these drawbacks can be alleviated effectively by using high- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> spacers without any severe degradation in the subthreshold analog/RF performance. In order to show the improvement in the device performance, we have studied the effect of high- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> spacers on different subthreshold analog figures of merit such as the transconductance, transconductance generation factor, output resistance, and the intrinsic gain for different values of <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> . Moreover, we have analyzed the RF performance as a function of intrinsic capacitance and resistance, transport delay, inductance, cutoff frequency, and the maximum oscillation frequency. In order to assess the gain bandwidth ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GBW</i> ) product, the circuit implementation of the UDG-NMOSFETs with different high- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> spacers was performed on a common source amplifier. Our results show an improvement in the GBW of about 38% for the devices with high- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> spacers compared to its low- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> counterpart.

Effect of underlap and gate length on device performance of an AlInN/GaN underlap MOSFET

We investigate the performance of an 18 nm gate length AlInN/GaN heterostructure underlap double gate MOSFET, using 2D Sentaurus TCAD simulation. The device uses lattice-matched wideband Al0.83In0.17N and narrowband GaN layers, along with high-k Al2O3 as the gate dielectric. The device has an ultrathin body and is designed according to the ITRS specifications. The simulation is done using the hydrodynamic model and interface traps are also considered. Due to the large two-dimensional electron gas (2DEG) density and high velocity, the maximal drain current density achieved is very high. Extensive device simulation of the major device performance metrics such as drain induced barrier lowering (DIBL), subthreshold slope (SS), delay, threshold voltage (Vt), Ion/Ioff ratio and energy delay product have been done for a wide range of gate and underlap lengths. Encouraging results for delay, Ion, DIBL and energy delay product are obtained. The results indicate that there is a need to optimize the Ioff and SS values for specific logic design. The proposed AlInN/GaN heterostructure underlap DG MOSFET shows excellent promise as one of the candidates to substitute currently used MOSFETs for future high speed applications.

Comparative assessment of III–V heterostructure and silicon underlap double gate MOSFETs

Comparative assessment of III–V heterostructure and silicon underlap DG-MOSFETs, is done using 2D Sentaurus TCAD simulation. III–V heterostructure device has narrow-band In0.53Ga0.47As and wide-band InP layers for body, and high-K gate dielectric. Density gradient model is used for simulation and interface traps are considered. Benchmarking of simulation results show that III–V device provides higher on current, lesser delay, lower energy-delay product and lower DIBL than silicon device. However III–V device has higher SS and lower Ion/Ioff than silicon device. The results indicate that there is a need to optimize the Ion/Ioff, SS and DIBL values for specific circuits.

Compact Modeling of a Generic Double-Gate MOSFET With Gate–S/D Underlap for Subthreshold Operation

In this brief, a new analytical model to compute the potential distribution in gate overlap and underlap regions of a generic double-gate (DG) MOSFET (valid for asymmetric features in front- and back-gate insulator thicknesses, gate bias, and gate work functions) for operation in the subthreshold condition is proposed. A closed form solution to 2-D Poisson's equation is obtained with approximation of parabolic potential function along vertical direction of the device. Conformal mapping technique is applied for modeling fringe electric field in the underlap regions. The proposed potential model is extended in deriving important device parameters such as threshold voltage, threshold voltage rolloff, DIBL, subthreshold swing, etc. Model predictions demonstrate that significant improvement in subthreshold operation can be achieved with 4T asymmetric underlap DG MOSFETs in comparison to 3T symmetric nonunderlap DG MOSFETs.

Impact of gate–source/drain channel architecture on the performance of an operational transconductance amplifier (OTA)

In this work, we report on the significance of gate–source/drain extension region (also known as underlap design) optimization in double gate (DG) FETs to improve the performance of an operational transconductance amplifier (OTA). It is demonstrated that high values of intrinsic voltage gain (AVO_OTA) > 55 dB and unity gain frequency (fT_OTA) ∼ 57 GHz in a folded cascode OTA can be achieved with gate-underlap channel design in 60 nm DG MOSFETs. These values correspond to 15 dB improvement in AVO_OTA and three fold enhancement in fT_OTA over a conventional non-underlap design. OTA performance based on underlap single gate SOI MOSFETs realized in ultra-thin body (UTB) and ultra-thin body BOX (UTBB) technologies is also evaluated. AVO_OTA values exhibited by a DG MOSFET-based OTA are 1.3–1.6 times higher as compared to a conventional UTB/UTBB single gate OTA. fT_OTA values for DG OTA are 10 GHz higher for UTB OTAs whereas a twofold improvement is observed with respect to UTBB OTAs. The simultaneous improvement in AVO_OTA and fT_OTA highlights the usefulness of underlap channel architecture in improving gain–bandwidth trade-off in analog circuit design. Underlap channel OTAs demonstrate high degree of tolerance to misalignment/oversize between front and back gates without compromising the performance, thus relaxing crucial process/technology-dependent parameters to achieve ‘idealized’ DG MOSFETs. Results show that underlap OTAs designed with a spacer-to-straggle (s/σ) ratio of 3.2 and operated below a bias current (IBIAS) of 80 µA demonstrate optimum performance. The present work provides new opportunities for realizing future ultra-wide band OTA design with underlap DG MOSFETs.

Optimizing Spacer-to-Straggle Ratio in Underlap Double Gate MOSFETs for Low Voltage Analog and Digital Circuits

In this work, we report on the significance of non-overlap channel architecture in nanoscale double gate (DG) FETs to improve performance of low-voltage analog and digital circuits. It is shown that the low-voltage operation of a cascoded Operational Transconductance Amplifier (OTA) and 6-T SRAM cell can be considerably enhanced using underlap gate-source/drain design. The present work provides new opportunities for realizing future low-voltage analog and digital circuits with underlap DG FETs.

Optimizing Spacer-to-Straggle Ratio in Underlap Double Gate MOSFETs for Low Voltage Analog and Digital Circuits

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How crucial is back gate misalignment/oversize in double gate MOSFETs for ultra-low-voltage analog/rf applications?

In the present work, by investigating the influence of source/drain (S/D) extension region engineering (also known as gate-underlap architecture) in planar Double Gate (DG) SOI MOSFETs, we offer new design insights to achieve high tolerance to gate misalignment/oversize in nanoscale devices for ultra-low-voltage (ULV) analog/rf applications. Our results show that (i) misaligned gate-underlap devices perform significantly better than DG devices with abrupt source/drain junctions with identical misalignment, (ii) misaligned gate underlap performance (with S/D optimization) exceeds perfectly aligned DG devices with abrupt S/D regions and (iii) 25% back gate misalignment can be tolerated without any significant degradation in cut–off frequency ( f T) and intrinsic voltage gain ( A VO). Gate-underlap DG devices designed with spacer-to-straggle ratio lying within the range 2.5 to 3.0 show best tolerance to misaligned/oversize back gate and indeed are better than self-aligned DG MOSFETs with non-underlap (abrupt) S/D regions. Impact of gate length and silicon film thickness scaling is also discussed. These results are very significant as the tolerable limit of misaligned/oversized back gate is considerably extended and the stringent process control requirements to achieve self-alignment can be relaxed for nanoscale planar ULV DG MOSFETs operating in weak-inversion region. The present work provides new opportunities for realizing future ULV analog/rf design with nanoscale gate–underlap DG MOSFETs.

Compact modeling of gate sidewall capacitance of DG-MOSFET

Recent studies show that the gate sidewall capacitance of an underlap double gate device plays an important role in the design and optimization of the device. To date, only semiempirical techniques are used to model this important capacitance. In this brief, the authors present an analytical model of the fringe capacitance and find out a geometry dependent quantity which determines the scaling of this capacitance

4638252 Circuit for detecting RF coil assembly position in an MR scanner

In analog and RF circuit applications Harmonic distortion (HD) is an important reliability issue that arises due to non-linear performance of devices. In this paper, the asymmetric underlap double gate MOSFET (AUDG-MOSFET) is analyzed for the HD with high-k spacers. In this analysis the devices are compared for their primary distortion components designated by the second order distortion (HD2), the third order distortion (HD3) and the total harmonic distortion (THD). The distortion characteristics of the device are studied as a function of the gate voltage (Vgs) and the transconductance generation factor (gm/Id) considering the influence of drain current (Id) and the transconductance (gm). A significant improvement on the HD of the device by using high-k spacers is inferred, thereby ascertaining better reliability for RF applications. In addition to this, the distortion in the output characteristics of Cascode and differential amplifier circuits designed with AUDG-MOSFET device is also analyzed in detail.